forked from OSchip/llvm-project
107 lines
3.8 KiB
LLVM
107 lines
3.8 KiB
LLVM
; RUN: opt %loadPolly -polly-detect-unprofitable -polly-scops -analyze < %s | FileCheck %s
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;
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; Verify the scalar x defined in a non-affine subregion is written as it
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; escapes the region. In this test the two conditionals inside the region
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; are expressed as one PHI nodes with three incoming values.
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;
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; void f(int *A, int b) {
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; for (int i = 0; i < 1024; i++) {
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; int x = 0;
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; if (A[i]) {
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; if (b > i)
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; x = 0;
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; else if (b < 2 * i)
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; x = i;
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; else
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; x = b;
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; }
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; A[i] = x;
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; }
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; }
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;
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; CHECK: Region: %bb2---%bb21
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; CHECK: Stmt_bb3__TO__bb18
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; CHECK: Domain :=
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; CHECK: { Stmt_bb3__TO__bb18[i0] :
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; CHECK-DAG: i0 >= 0
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; CHECK-DAG: and
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; CHECK-DAG: i0 <= 1023
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; CHECK: }
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; CHECK: Schedule :=
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; CHECK: { Stmt_bb3__TO__bb18[i0] -> [i0, 0] };
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; CHECK: ReadAccess := [Reduction Type: NONE] [Scalar: 0]
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; CHECK: { Stmt_bb3__TO__bb18[i0] -> MemRef_A[i0] };
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; CHECK: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1]
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; CHECK: { Stmt_bb3__TO__bb18[i0] -> MemRef_x_2__phi[] };
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; CHECK: MayWriteAccess := [Reduction Type: NONE] [Scalar: 1]
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; CHECK: { Stmt_bb3__TO__bb18[i0] -> MemRef_x_2__phi[] };
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; CHECK: MayWriteAccess := [Reduction Type: NONE] [Scalar: 1]
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; CHECK: { Stmt_bb3__TO__bb18[i0] -> MemRef_x_2__phi[] };
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; CHECK: MayWriteAccess := [Reduction Type: NONE] [Scalar: 1]
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; CHECK: { Stmt_bb3__TO__bb18[i0] -> MemRef_x_2__phi[] };
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; CHECK: Stmt_bb18
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; CHECK: Domain :=
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; CHECK: { Stmt_bb18[i0] :
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; CHECK-DAG: i0 >= 0
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; CHECK-DAG: and
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; CHECK-DAG: i0 <= 1023
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; CHECK: }
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; CHECK: Schedule :=
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; CHECK: { Stmt_bb18[i0] -> [i0, 1] };
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; CHECK: ReadAccess := [Reduction Type: NONE] [Scalar: 1]
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; CHECK: { Stmt_bb18[i0] -> MemRef_x_2__phi[] };
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; CHECK: MustWriteAccess := [Reduction Type: NONE] [Scalar: 0]
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; CHECK: { Stmt_bb18[i0] -> MemRef_A[i0] };
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;
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target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
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define void @f(i32* %A, i32 %b) {
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bb:
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%tmp = sext i32 %b to i64
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%tmp1 = sext i32 %b to i64
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br label %bb2
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bb2: ; preds = %bb20, %bb
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%indvars.iv = phi i64 [ %indvars.iv.next, %bb20 ], [ 0, %bb ]
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%exitcond = icmp ne i64 %indvars.iv, 1024
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br i1 %exitcond, label %bb3, label %bb21
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bb3: ; preds = %bb2
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%tmp4 = getelementptr inbounds i32, i32* %A, i64 %indvars.iv
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%tmp5 = load i32, i32* %tmp4, align 4
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%tmp6 = icmp eq i32 %tmp5, 0
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br i1 %tmp6, label %bb18, label %bb7
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bb7: ; preds = %bb3
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%tmp8 = icmp slt i64 %indvars.iv, %tmp
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br i1 %tmp8, label %bb9, label %bb10
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bb9: ; preds = %bb7
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br label %bb18
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bb10: ; preds = %bb7
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%tmp11 = shl nsw i64 %indvars.iv, 1
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%tmp12 = icmp sgt i64 %tmp11, %tmp1
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br i1 %tmp12, label %bb13, label %bb15
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bb13: ; preds = %bb10
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%tmp14 = trunc i64 %indvars.iv to i32
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br label %bb18
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bb15: ; preds = %bb10
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br label %bb18
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bb18: ; preds = %bb3, %bb13, %bb15, %bb9
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%x.2 = phi i32 [ 0, %bb9 ], [ %tmp14, %bb13 ], [ %b, %bb15 ], [ 0, %bb3 ]
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%tmp19 = getelementptr inbounds i32, i32* %A, i64 %indvars.iv
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store i32 %x.2, i32* %tmp19, align 4
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br label %bb20
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bb20: ; preds = %bb18
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%indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
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br label %bb2
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bb21: ; preds = %bb2
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ret void
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}
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