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406 lines
14 KiB
ReStructuredText
406 lines
14 KiB
ReStructuredText
==============================
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User Guide for AMDGPU Back-end
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==============================
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Introduction
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============
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The AMDGPU back-end provides ISA code generation for AMD GPUs, starting with
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the R600 family up until the current Volcanic Islands (GCN Gen 3).
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Refer to `AMDGPU section in Architecture & Platform Information for Compiler Writers <CompilerWriterInfo.html#amdgpu>`_
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for additional documentation.
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Conventions
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===========
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Address Spaces
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--------------
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The AMDGPU back-end uses the following address space mapping:
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================== =================== ==============
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LLVM Address Space DWARF Address Space Memory Space
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================== =================== ==============
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0 1 Private
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1 N/A Global
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2 N/A Constant
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3 2 Local
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4 N/A Generic (Flat)
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5 N/A Region
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================== =================== ==============
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The terminology in the table, aside from the region memory space, is from the
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OpenCL standard.
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LLVM Address Space is used throughout LLVM (for example, in LLVM IR). DWARF
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Address Space is emitted in DWARF, and is used by tools, such as debugger,
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profiler and others.
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Trap Handler ABI
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----------------
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The OS element of the target triple controls the trap handler behavior.
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HSA OS
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^^^^^^
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For code objects generated by AMDGPU back-end for the HSA OS, the runtime
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installs a trap handler that supports the s_trap instruction with the following
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usage:
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+--------------+-------------+-------------------+----------------------------+
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|Usage |Code Sequence|Trap Handler Inputs|Description |
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+==============+=============+===================+============================+
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|reserved |s_trap 0x00 | |Reserved by hardware. |
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+--------------+-------------+-------------------+----------------------------+
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|HSA debugtrap |s_trap 0x01 |SGPR0-1: queue_ptr |Reserved for HSA debugtrap |
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|(arg) | |VGPR0: arg |intrinsic (not implemented).|
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+--------------+-------------+-------------------+----------------------------+
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|llvm.trap |s_trap 0x02 |SGPR0-1: queue_ptr |Causes dispatch to be |
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| | | |terminated and its |
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| | | |associated queue put into |
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| | | |the error state. |
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+--------------+-------------+-------------------+----------------------------+
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|llvm.debugtrap| s_trap 0x03 |SGPR0-1: queue_ptr |If debugger not installed |
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| | | |handled same as llvm.trap. |
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+--------------+-------------+-------------------+----------------------------+
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|debugger |s_trap 0x07 | |Reserved for debugger |
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|breakpoint | | |breakpoints. |
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+--------------+-------------+-------------------+----------------------------+
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|debugger |s_trap 0x08 | |Reserved for debugger. |
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+--------------+-------------+-------------------+----------------------------+
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|debugger |s_trap 0xfe | |Reserved for debugger. |
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+--------------+-------------+-------------------+----------------------------+
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|debugger |s_trap 0xff | |Reserved for debugger. |
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+--------------+-------------+-------------------+----------------------------+
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Non-HSA OS
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^^^^^^^^^^
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For code objects generated by AMDGPU back-end for non-HSA OS, the runtime does
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not install a trap handler. The llvm.trap and llvm.debugtrap instructions are
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handler as follows:
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=============== ============= ===============================================
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Usage Code Sequence Description
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=============== ============= ===============================================
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llvm.trap s_endpgm Causes wavefront to be terminated.
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llvm.debugtrap Nothing Compiler warning generated that there is no trap handler installed.
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=============== ============= ===============================================
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Assembler
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=========
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AMDGPU backend has LLVM-MC based assembler which is currently in development.
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It supports Southern Islands ISA, Sea Islands and Volcanic Islands.
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This document describes general syntax for instructions and operands. For more
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information about instructions, their semantics and supported combinations
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of operands, refer to one of Instruction Set Architecture manuals.
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An instruction has the following syntax (register operands are
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normally comma-separated while extra operands are space-separated):
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*<opcode> <register_operand0>, ... <extra_operand0> ...*
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Operands
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--------
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The following syntax for register operands is supported:
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* SGPR registers: s0, ... or s[0], ...
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* VGPR registers: v0, ... or v[0], ...
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* TTMP registers: ttmp0, ... or ttmp[0], ...
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* Special registers: exec (exec_lo, exec_hi), vcc (vcc_lo, vcc_hi), flat_scratch (flat_scratch_lo, flat_scratch_hi)
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* Special trap registers: tba (tba_lo, tba_hi), tma (tma_lo, tma_hi)
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* Register pairs, quads, etc: s[2:3], v[10:11], ttmp[5:6], s[4:7], v[12:15], ttmp[4:7], s[8:15], ...
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* Register lists: [s0, s1], [ttmp0, ttmp1, ttmp2, ttmp3]
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* Register index expressions: v[2*2], s[1-1:2-1]
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* 'off' indicates that an operand is not enabled
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The following extra operands are supported:
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* offset, offset0, offset1
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* idxen, offen bits
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* glc, slc, tfe bits
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* waitcnt: integer or combination of counter values
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* VOP3 modifiers:
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- abs (\| \|), neg (\-)
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* DPP modifiers:
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- row_shl, row_shr, row_ror, row_rol
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- row_mirror, row_half_mirror, row_bcast
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- wave_shl, wave_shr, wave_ror, wave_rol, quad_perm
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- row_mask, bank_mask, bound_ctrl
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* SDWA modifiers:
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- dst_sel, src0_sel, src1_sel (BYTE_N, WORD_M, DWORD)
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- dst_unused (UNUSED_PAD, UNUSED_SEXT, UNUSED_PRESERVE)
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- abs, neg, sext
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DS Instructions Examples
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------------------------
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.. code-block:: nasm
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ds_add_u32 v2, v4 offset:16
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ds_write_src2_b64 v2 offset0:4 offset1:8
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ds_cmpst_f32 v2, v4, v6
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ds_min_rtn_f64 v[8:9], v2, v[4:5]
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For full list of supported instructions, refer to "LDS/GDS instructions" in ISA Manual.
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FLAT Instruction Examples
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--------------------------
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.. code-block:: nasm
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flat_load_dword v1, v[3:4]
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flat_store_dwordx3 v[3:4], v[5:7]
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flat_atomic_swap v1, v[3:4], v5 glc
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flat_atomic_cmpswap v1, v[3:4], v[5:6] glc slc
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flat_atomic_fmax_x2 v[1:2], v[3:4], v[5:6] glc
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For full list of supported instructions, refer to "FLAT instructions" in ISA Manual.
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MUBUF Instruction Examples
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---------------------------
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.. code-block:: nasm
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buffer_load_dword v1, off, s[4:7], s1
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buffer_store_dwordx4 v[1:4], v2, ttmp[4:7], s1 offen offset:4 glc tfe
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buffer_store_format_xy v[1:2], off, s[4:7], s1
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buffer_wbinvl1
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buffer_atomic_inc v1, v2, s[8:11], s4 idxen offset:4 slc
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For full list of supported instructions, refer to "MUBUF Instructions" in ISA Manual.
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SMRD/SMEM Instruction Examples
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-------------------------------
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.. code-block:: nasm
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s_load_dword s1, s[2:3], 0xfc
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s_load_dwordx8 s[8:15], s[2:3], s4
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s_load_dwordx16 s[88:103], s[2:3], s4
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s_dcache_inv_vol
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s_memtime s[4:5]
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For full list of supported instructions, refer to "Scalar Memory Operations" in ISA Manual.
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SOP1 Instruction Examples
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--------------------------
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.. code-block:: nasm
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s_mov_b32 s1, s2
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s_mov_b64 s[0:1], 0x80000000
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s_cmov_b32 s1, 200
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s_wqm_b64 s[2:3], s[4:5]
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s_bcnt0_i32_b64 s1, s[2:3]
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s_swappc_b64 s[2:3], s[4:5]
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s_cbranch_join s[4:5]
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For full list of supported instructions, refer to "SOP1 Instructions" in ISA Manual.
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SOP2 Instruction Examples
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-------------------------
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.. code-block:: nasm
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s_add_u32 s1, s2, s3
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s_and_b64 s[2:3], s[4:5], s[6:7]
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s_cselect_b32 s1, s2, s3
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s_andn2_b32 s2, s4, s6
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s_lshr_b64 s[2:3], s[4:5], s6
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s_ashr_i32 s2, s4, s6
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s_bfm_b64 s[2:3], s4, s6
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s_bfe_i64 s[2:3], s[4:5], s6
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s_cbranch_g_fork s[4:5], s[6:7]
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For full list of supported instructions, refer to "SOP2 Instructions" in ISA Manual.
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SOPC Instruction Examples
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--------------------------
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.. code-block:: nasm
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s_cmp_eq_i32 s1, s2
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s_bitcmp1_b32 s1, s2
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s_bitcmp0_b64 s[2:3], s4
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s_setvskip s3, s5
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For full list of supported instructions, refer to "SOPC Instructions" in ISA Manual.
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SOPP Instruction Examples
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--------------------------
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.. code-block:: nasm
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s_barrier
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s_nop 2
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s_endpgm
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s_waitcnt 0 ; Wait for all counters to be 0
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s_waitcnt vmcnt(0) & expcnt(0) & lgkmcnt(0) ; Equivalent to above
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s_waitcnt vmcnt(1) ; Wait for vmcnt counter to be 1.
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s_sethalt 9
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s_sleep 10
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s_sendmsg 0x1
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s_sendmsg sendmsg(MSG_INTERRUPT)
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s_trap 1
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For full list of supported instructions, refer to "SOPP Instructions" in ISA Manual.
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Unless otherwise mentioned, little verification is performed on the operands
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of SOPP Instructions, so it is up to the programmer to be familiar with the
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range or acceptable values.
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Vector ALU Instruction Examples
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-------------------------------
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For vector ALU instruction opcodes (VOP1, VOP2, VOP3, VOPC, VOP_DPP, VOP_SDWA),
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the assembler will automatically use optimal encoding based on its operands.
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To force specific encoding, one can add a suffix to the opcode of the instruction:
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* _e32 for 32-bit VOP1/VOP2/VOPC
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* _e64 for 64-bit VOP3
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* _dpp for VOP_DPP
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* _sdwa for VOP_SDWA
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VOP1/VOP2/VOP3/VOPC examples:
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.. code-block:: nasm
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v_mov_b32 v1, v2
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v_mov_b32_e32 v1, v2
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v_nop
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v_cvt_f64_i32_e32 v[1:2], v2
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v_floor_f32_e32 v1, v2
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v_bfrev_b32_e32 v1, v2
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v_add_f32_e32 v1, v2, v3
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v_mul_i32_i24_e64 v1, v2, 3
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v_mul_i32_i24_e32 v1, -3, v3
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v_mul_i32_i24_e32 v1, -100, v3
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v_addc_u32 v1, s[0:1], v2, v3, s[2:3]
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v_max_f16_e32 v1, v2, v3
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VOP_DPP examples:
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.. code-block:: nasm
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v_mov_b32 v0, v0 quad_perm:[0,2,1,1]
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v_sin_f32 v0, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0
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v_mov_b32 v0, v0 wave_shl:1
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v_mov_b32 v0, v0 row_mirror
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v_mov_b32 v0, v0 row_bcast:31
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v_mov_b32 v0, v0 quad_perm:[1,3,0,1] row_mask:0xa bank_mask:0x1 bound_ctrl:0
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v_add_f32 v0, v0, |v0| row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0
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v_max_f16 v1, v2, v3 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0
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VOP_SDWA examples:
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.. code-block:: nasm
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v_mov_b32 v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PRESERVE src0_sel:DWORD
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v_min_u32 v200, v200, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
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v_sin_f32 v0, v0 dst_unused:UNUSED_PAD src0_sel:WORD_1
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v_fract_f32 v0, |v0| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
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v_cmpx_le_u32 vcc, v1, v2 src0_sel:BYTE_2 src1_sel:WORD_0
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For full list of supported instructions, refer to "Vector ALU instructions".
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HSA Code Object Directives
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--------------------------
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AMDGPU ABI defines auxiliary data in output code object. In assembly source,
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one can specify them with assembler directives.
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.hsa_code_object_version major, minor
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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*major* and *minor* are integers that specify the version of the HSA code
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object that will be generated by the assembler.
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.hsa_code_object_isa [major, minor, stepping, vendor, arch]
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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*major*, *minor*, and *stepping* are all integers that describe the instruction
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set architecture (ISA) version of the assembly program.
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*vendor* and *arch* are quoted strings. *vendor* should always be equal to
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"AMD" and *arch* should always be equal to "AMDGPU".
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By default, the assembler will derive the ISA version, *vendor*, and *arch*
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from the value of the -mcpu option that is passed to the assembler.
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.amdgpu_hsa_kernel (name)
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^^^^^^^^^^^^^^^^^^^^^^^^^
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This directives specifies that the symbol with given name is a kernel entry point
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(label) and the object should contain corresponding symbol of type STT_AMDGPU_HSA_KERNEL.
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.amd_kernel_code_t
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^^^^^^^^^^^^^^^^^^
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This directive marks the beginning of a list of key / value pairs that are used
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to specify the amd_kernel_code_t object that will be emitted by the assembler.
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The list must be terminated by the *.end_amd_kernel_code_t* directive. For
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any amd_kernel_code_t values that are unspecified a default value will be
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used. The default value for all keys is 0, with the following exceptions:
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- *kernel_code_version_major* defaults to 1.
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- *machine_kind* defaults to 1.
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- *machine_version_major*, *machine_version_minor*, and
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*machine_version_stepping* are derived from the value of the -mcpu option
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that is passed to the assembler.
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- *kernel_code_entry_byte_offset* defaults to 256.
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- *wavefront_size* defaults to 6.
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- *kernarg_segment_alignment*, *group_segment_alignment*, and
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*private_segment_alignment* default to 4. Note that alignments are specified
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as a power of two, so a value of **n** means an alignment of 2^ **n**.
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The *.amd_kernel_code_t* directive must be placed immediately after the
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function label and before any instructions.
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For a full list of amd_kernel_code_t keys, refer to AMDGPU ABI document,
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comments in lib/Target/AMDGPU/AmdKernelCodeT.h and test/CodeGen/AMDGPU/hsa.s.
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Here is an example of a minimal amd_kernel_code_t specification:
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.. code-block:: none
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.hsa_code_object_version 1,0
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.hsa_code_object_isa
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.hsatext
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.globl hello_world
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.p2align 8
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.amdgpu_hsa_kernel hello_world
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hello_world:
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.amd_kernel_code_t
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enable_sgpr_kernarg_segment_ptr = 1
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is_ptr64 = 1
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compute_pgm_rsrc1_vgprs = 0
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compute_pgm_rsrc1_sgprs = 0
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compute_pgm_rsrc2_user_sgpr = 2
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kernarg_segment_byte_size = 8
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wavefront_sgpr_count = 2
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workitem_vgpr_count = 3
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.end_amd_kernel_code_t
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s_load_dwordx2 s[0:1], s[0:1] 0x0
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v_mov_b32 v0, 3.14159
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s_waitcnt lgkmcnt(0)
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v_mov_b32 v1, s0
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v_mov_b32 v2, s1
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flat_store_dword v[1:2], v0
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s_endpgm
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.Lfunc_end0:
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.size hello_world, .Lfunc_end0-hello_world
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