llvm-project/llvm/lib/Target/AArch64/GISel
Raul Tambre e887d0e89b [AArch64][GlobalISel] Handle rtcGPR64RegClassID in AArch64RegisterBankInfo::getRegBankFromRegClass()
TargetRegisterInfo::getMinimalPhysRegClass() returns rtcGPR64RegClassID for X16
and X17, as it's the last matching class. This in turn gets passed to
AArch64RegisterBankInfo::getRegBankFromRegClass(), which hits an unreachable.

It seems sensible to handle this case, so copies from X16 and X17 work.
Copying from X17 is used in inline assembly in libunwind for pointer
authentication.

Differential Revision: https://reviews.llvm.org/D85720
2020-08-19 12:52:30 -07:00
..
AArch64CallLowering.cpp AArch64: Use Register 2020-07-22 14:14:44 -04:00
AArch64CallLowering.h [SVE][CodeGen] Fix bug when falling back to DAG ISel 2020-07-07 09:23:04 +01:00
AArch64InstructionSelector.cpp AArch64/GlobalISel: Fix verifier error after selecting returnaddress 2020-08-06 13:18:05 -04:00
AArch64LegalizerInfo.cpp [HWASan] [GlobalISel] Add +tagged-globals backend feature for GlobalISel 2020-08-03 14:28:44 -07:00
AArch64LegalizerInfo.h GlobalISel: Pass LegalizerHelper to custom legalize callbacks 2020-06-18 17:17:38 -04:00
AArch64PostLegalizerCombiner.cpp [AArch64][GlobalISel] Selection support for vector DUP[X]lane instructions. 2020-07-29 11:41:37 -07:00
AArch64PreLegalizerCombiner.cpp [gicombiner] Allow generated combiners to store additional members 2020-06-16 14:47:04 -07:00
AArch64RegisterBankInfo.cpp [AArch64][GlobalISel] Handle rtcGPR64RegClassID in AArch64RegisterBankInfo::getRegBankFromRegClass() 2020-08-19 12:52:30 -07:00
AArch64RegisterBankInfo.h [AArch64] Move RegisterBankInfo.cpp/h to GISel. 2020-06-09 23:26:25 -07:00