forked from OSchip/llvm-project
89 lines
3.5 KiB
TableGen
89 lines
3.5 KiB
TableGen
// WebAssemblyInstrInfo.td-Describe the WebAssembly Instructions-*- tablegen -*-
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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///
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/// \file
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/// \brief WebAssembly Instruction definitions.
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///
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// WebAssembly Instruction Predicate Definitions.
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//===----------------------------------------------------------------------===//
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def HasAddr32 : Predicate<"!Subtarget->hasAddr64()">;
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def HasAddr64 : Predicate<"Subtarget->hasAddr64()">;
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def HasSIMD128 : Predicate<"Subtarget->hasSIMD128()">,
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AssemblerPredicate<"FeatureSIMD128", "simd128">;
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//===----------------------------------------------------------------------===//
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// WebAssembly-specific DAG Node Types.
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//===----------------------------------------------------------------------===//
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def SDT_WebAssemblyArgument : SDTypeProfile<1, 1, [SDTCisVT<1, i32>]>;
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def SDT_WebAssemblyReturn : SDTypeProfile<0, -1, []>;
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//===----------------------------------------------------------------------===//
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// WebAssembly-specific DAG Nodes.
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//===----------------------------------------------------------------------===//
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def WebAssemblyargument : SDNode<"WebAssemblyISD::ARGUMENT",
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SDT_WebAssemblyArgument>;
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def WebAssemblyreturn : SDNode<"WebAssemblyISD::RETURN",
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SDT_WebAssemblyReturn,
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[SDNPHasChain, SDNPSideEffect]>;
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//===----------------------------------------------------------------------===//
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// WebAssembly-specific Operands.
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//===----------------------------------------------------------------------===//
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/*
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* TODO(jfb): Add the following.
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*
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* get_local: read the current value of a local variable
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* set_local: set the current value of a local variable
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*/
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//===----------------------------------------------------------------------===//
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// WebAssembly Instruction Format Definitions.
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//===----------------------------------------------------------------------===//
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include "WebAssemblyInstrFormats.td"
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multiclass ARGUMENT<WebAssemblyRegClass vt> {
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def ARGUMENT_#vt : I<(outs vt:$res), (ins i32imm:$argno),
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[(set vt:$res, (WebAssemblyargument timm:$argno))]>;
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}
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defm : ARGUMENT<Int32>;
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defm : ARGUMENT<Int64>;
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defm : ARGUMENT<Float32>;
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defm : ARGUMENT<Float64>;
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def Immediate_I32 : I<(outs Int32:$res), (ins i32imm:$imm),
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[(set Int32:$res, imm:$imm)]>;
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def Immediate_I64 : I<(outs Int64:$res), (ins i64imm:$imm),
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[(set Int64:$res, imm:$imm)]>;
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def Immediate_F32 : I<(outs Float32:$res), (ins f32imm:$imm),
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[(set Float32:$res, fpimm:$imm)]>;
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def Immediate_F64 : I<(outs Float64:$res), (ins f64imm:$imm),
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[(set Float64:$res, fpimm:$imm)]>;
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//===----------------------------------------------------------------------===//
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// Additional sets of instructions.
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//===----------------------------------------------------------------------===//
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include "WebAssemblyInstrMemory.td"
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include "WebAssemblyInstrCall.td"
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include "WebAssemblyInstrControl.td"
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include "WebAssemblyInstrInteger.td"
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include "WebAssemblyInstrFloat.td"
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include "WebAssemblyInstrConv.td"
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include "WebAssemblyInstrAtomics.td"
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include "WebAssemblyInstrSIMD.td"
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