forked from OSchip/llvm-project
72 lines
1.9 KiB
TableGen
72 lines
1.9 KiB
TableGen
//===- SparcV9_F2.td - SparcV9 Format 2 instructions -------*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by the LLVM research group and is distributed under
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Format #2 classes
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//
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class F2 : InstV9 { // Format 2 instructions
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bits<3> op2;
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let op = 0; // Op = 0
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let Inst{24-22} = op2;
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}
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// Format 2.1 instructions
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class F2_1<string name> : F2 {
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bits<22> imm;
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bits<5> rd;
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let Name = name;
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let Inst{29-25} = rd;
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let Inst{21-0} = imm;
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}
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class F2_br : F2 { // Format 2 Branch instruction
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let isBranch = 1; // All instances are branch instructions
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}
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class F2_2<bits<4> cond, string name> : F2_br { // Format 2.2 instructions
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bits<22> disp;
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bit annul = 0; // currently unused by SparcV9 backend
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let Name = name;
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let Inst{29} = annul;
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let Inst{28-25} = cond;
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let Inst{21-0} = disp;
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}
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class F2_3<bits<4> cond, string name> : F2_br { // Format 2.3 instructions
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bits<2> cc;
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bits<19> disp;
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bit predict = 1;
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bit annul = 0; // currently unused by SparcV9 backend
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let Name = name;
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let Inst{29} = annul;
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let Inst{28-25} = cond;
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let Inst{21-20} = cc;
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let Inst{19} = predict;
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let Inst{18-0} = disp;
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}
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class F2_4<bits<3> rcond, string name> : F2_br { // Format 2.4 instructions
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bits<5> rs1;
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bits<16> disp;
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bit predict = 1;
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bit annul = 0; // currently unused by SparcV9 backend
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let Name = name;
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let Inst{29} = annul;
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let Inst{28} = 0;
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let Inst{27-25} = rcond;
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let Inst{21-20} = disp{15-14};
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let Inst{19} = predict;
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let Inst{18-14} = rs1;
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let Inst{13-0 } = disp{13-0};
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}
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