forked from OSchip/llvm-project
53 lines
1.9 KiB
TableGen
53 lines
1.9 KiB
TableGen
//===- SparcV9.td - Target Description for SparcV9 Target --*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by the LLVM research group and is distributed under
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// TableGen target description file for the SparcV9. This is currently used
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// primarily to generate part of the SparcV9CodeEmitter automatically.
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Target-independent interfaces which we are implementing
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//===----------------------------------------------------------------------===//
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include "../Target.td"
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//===----------------------------------------------------------------------===//
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// Register File Description
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//===----------------------------------------------------------------------===//
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include "SparcV9RegisterInfo.td"
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//===----------------------------------------------------------------------===//
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// Instruction Descriptions
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//===----------------------------------------------------------------------===//
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include "SparcV9InstrInfo.td"
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def SparcV9InstrInfo : InstrInfo {
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// Define how we want to layout our TargetSpecific information field.
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let TSFlagsFields = [];
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let TSFlagsShifts = [];
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}
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//===----------------------------------------------------------------------===//
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// Declare the target which we are implementing
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//===----------------------------------------------------------------------===//
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def SparcV9 : Target {
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// FIXME: Specify the callee saved registers.
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let CalleeSavedRegisters = [];
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// Pointers are 64-bits in size.
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let PointerType = i64;
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// Information about the instructions...
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let InstructionSet = SparcV9InstrInfo;
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}
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