forked from OSchip/llvm-project
94 lines
3.1 KiB
C++
94 lines
3.1 KiB
C++
//===- LICMTest.cpp - LICM unit tests -------------------------------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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#include "llvm/Analysis/ScalarEvolution.h"
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#include "llvm/AsmParser/Parser.h"
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#include "llvm/IR/Module.h"
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#include "llvm/Passes/PassBuilder.h"
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#include "llvm/Support/SourceMgr.h"
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#include "llvm/Testing/Support/Error.h"
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#include "llvm/Transforms/Scalar/LICM.h"
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#include "gtest/gtest.h"
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namespace llvm {
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TEST(LICMTest, TestSCEVInvalidationOnHoisting) {
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LLVMContext Ctx;
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ModulePassManager MPM;
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PassBuilder PB;
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LoopAnalysisManager LAM;
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FunctionAnalysisManager FAM;
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CGSCCAnalysisManager CGAM;
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ModuleAnalysisManager MAM;
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PB.registerModuleAnalyses(MAM);
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PB.registerCGSCCAnalyses(CGAM);
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PB.registerFunctionAnalyses(FAM);
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PB.registerLoopAnalyses(LAM);
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PB.crossRegisterProxies(LAM, FAM, CGAM, MAM);
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StringRef PipelineStr = "require<opt-remark-emit>,loop(licm)";
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ASSERT_THAT_ERROR(PB.parsePassPipeline(MPM, PipelineStr), Succeeded());
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SMDiagnostic Error;
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StringRef Text = R"(
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define void @foo(i64* %ptr) {
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entry:
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br label %loop
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loop:
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%iv = phi i64 [ 0, %entry ], [ %iv.inc, %loop ]
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%n = load i64, i64* %ptr, !invariant.load !0
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%iv.inc = add i64 %iv, 1
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%cmp = icmp ult i64 %iv.inc, %n
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br i1 %cmp, label %loop, label %exit
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exit:
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ret void
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}
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!0 = !{}
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)";
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std::unique_ptr<Module> M = parseAssemblyString(Text, Error, Ctx);
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ASSERT_TRUE(M);
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Function *F = M->getFunction("foo");
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ScalarEvolution &SE = FAM.getResult<ScalarEvolutionAnalysis>(*F);
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BasicBlock &EntryBB = F->getEntryBlock();
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BasicBlock *LoopBB = EntryBB.getUniqueSuccessor();
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// Select `load i64, i64* %ptr`.
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Instruction *IBefore = LoopBB->getFirstNonPHI();
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// Make sure the right instruction was selected.
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ASSERT_TRUE(isa<LoadInst>(IBefore));
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// Upon this query SCEV caches disposition of <load i64, i64* %ptr> SCEV.
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ASSERT_EQ(SE.getBlockDisposition(SE.getSCEV(IBefore), LoopBB),
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ScalarEvolution::BlockDisposition::DominatesBlock);
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MPM.run(*M, MAM);
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// Select `load i64, i64* %ptr` after it was hoisted.
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Instruction *IAfter = EntryBB.getFirstNonPHI();
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// Make sure the right instruction was selected.
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ASSERT_TRUE(isa<LoadInst>(IAfter));
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ScalarEvolution::BlockDisposition DispositionBeforeInvalidation =
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SE.getBlockDisposition(SE.getSCEV(IAfter), LoopBB);
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SE.forgetValue(IAfter);
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ScalarEvolution::BlockDisposition DispositionAfterInvalidation =
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SE.getBlockDisposition(SE.getSCEV(IAfter), LoopBB);
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// If LICM have properly invalidated SCEV,
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// 1. SCEV of <load i64, i64* %ptr> should properly dominate the "loop" BB,
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// 2. extra invalidation shouldn't change result of the query.
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EXPECT_EQ(DispositionBeforeInvalidation,
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ScalarEvolution::BlockDisposition::ProperlyDominatesBlock);
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EXPECT_EQ(DispositionBeforeInvalidation, DispositionAfterInvalidation);
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}
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}
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