forked from OSchip/llvm-project
a16bd4f9f2
Summary: Add an initial GlobalISel skeleton for RISCV. It can only run ir translator for `ret void`. Patch by Andrew Wei Reviewers: asb, sabuasal, apazos, lenary, simoncook, lewis-revill, edward-jones, rogfer01, xiangzhai, rovka, Petar.Avramovic, mgorny, dsanders Reviewed By: dsanders Subscribers: pzheng, s.egerton, dsanders, hiraditya, rbar, johnrusso, niosHD, kito-cheng, shiva0217, jrtc27, MaskRay, zzheng, MartinMosbeck, brucehoult, the_o, PkmX, jocewei, psnobl, benna, Jim, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D65219 llvm-svn: 369467 |
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.. | ||
AArch64 | ||
AMDGPU | ||
ARC | ||
ARM | ||
AVR | ||
BPF | ||
Generic | ||
Hexagon | ||
Inputs | ||
Lanai | ||
MIR | ||
MSP430 | ||
Mips | ||
NVPTX | ||
PowerPC | ||
RISCV | ||
SPARC | ||
SystemZ | ||
Thumb | ||
Thumb2 | ||
WebAssembly | ||
WinCFGuard | ||
WinEH | ||
X86 | ||
XCore |