forked from OSchip/llvm-project
b22f751fa7
Currently it's not possible to access MCSubtargetInfo from a TgtMCAsmBackend. D20830 threaded an MCSubtargetInfo reference through MCAsmBackend::relaxInstruction, but this isn't the only function that would benefit from access. This patch removes the Triple and CPUString arguments from createMCAsmBackend and replaces them with MCSubtargetInfo. This patch just changes the interface without making any intentional functional changes. Once in, several cleanups are possible: * Get rid of the awkward MCSubtargetInfo handling in ARMAsmBackend * Support 16-bit instructions when valid in MipsAsmBackend::writeNopData * Get rid of the CPU string parsing in X86AsmBackend and just use a SubtargetFeature for HasNopl * Emit 16-bit nops in RISCVAsmBackend::writeNopData if the compressed instruction set extension is enabled (see D41221) This change initially exposed PR35686, which has since been resolved in r321026. Differential Revision: https://reviews.llvm.org/D41349 llvm-svn: 321692 |
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| .. | ||
| CMakeLists.txt | ||
| LLVMBuild.txt | ||
| SystemZMCAsmBackend.cpp | ||
| SystemZMCAsmInfo.cpp | ||
| SystemZMCAsmInfo.h | ||
| SystemZMCCodeEmitter.cpp | ||
| SystemZMCFixups.h | ||
| SystemZMCObjectWriter.cpp | ||
| SystemZMCTargetDesc.cpp | ||
| SystemZMCTargetDesc.h | ||