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llvm-project/llvm/lib/Target/RISCV/MCTargetDesc
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Sameer AbuAsal e01e711c64 [RISCV] Tail calls don't need to save return address 
Summary:
 When expanding the PseudoTail in expandFunctionCall() we were using X6
 to save the return address. Since this is a tail call the return
 address is not needed, this patch replaces it with X0 to be ignored.

 This matches the behaviour listed in the ISA V2.2 document page 110.
 tail offset -----> jalr x0, x6, offset

 GCC exhibits the same behavior.

Reviewers: apazos, asb, mgrang

Reviewed By: asb

Subscribers: rbar, johnrusso, simoncook, niosHD, kito-cheng, shiva0217, zzheng, edward-jones, rogfer01

Differential Revision: https://reviews.llvm.org/D48343

llvm-svn: 335239
 		2018-06-21 14:37:09 +00:00
..
CMakeLists.txt Revert "[RISCV] implement li pseudo instruction" 2018-04-18 19:02:31 +00:00
LLVMBuild.txt [RISCV] Add RISCVInstPrinter and basic MC assembler tests 2017-08-15 13:08:29 +00:00
RISCVAsmBackend.cpp Fix compilation of WebAssembly and RISCV after r334078 2018-06-06 10:57:50 +00:00
RISCVBaseInfo.h [RISCV] MC layer support for load/store instructions of the C (compressed) extension 2017-12-07 12:50:32 +00:00
RISCVELFObjectWriter.cpp [RISCV] Support linker relax function call from auipc and jalr to jal 2018-05-24 06:21:23 +00:00
RISCVELFStreamer.cpp [RISCV] Support .option rvc and norvc assembler directives 2018-05-11 17:30:28 +00:00
RISCVELFStreamer.h [RISCV] Support .option rvc and norvc assembler directives 2018-05-11 17:30:28 +00:00
RISCVFixupKinds.h [RISCV] Support linker relax function call from auipc and jalr to jal 2018-05-24 06:21:23 +00:00
RISCVMCAsmInfo.cpp [RISCV] Add support for .half, .hword, .word, .dword directives 2018-05-17 05:58:08 +00:00
RISCVMCAsmInfo.h
…
RISCVMCCodeEmitter.cpp [RISCV] Tail calls don't need to save return address 2018-06-21 14:37:09 +00:00
RISCVMCExpr.cpp [RISCV] Add symbol diff relocation support for RISC-V 2018-05-23 12:36:18 +00:00
RISCVMCExpr.h [RISCV] Support "call" pseudoinstruction in the MC layer 2018-04-25 14:18:55 +00:00
RISCVMCTargetDesc.cpp [RISCV] Support .option rvc and norvc assembler directives 2018-05-11 17:30:28 +00:00
RISCVMCTargetDesc.h MC: Separate creating a generic object writer from creating a target object writer. NFCI. 2018-05-21 19:20:29 +00:00
RISCVTargetStreamer.cpp [RISCV] Support .option rvc and norvc assembler directives 2018-05-11 17:30:28 +00:00
RISCVTargetStreamer.h [RISCV] Support .option rvc and norvc assembler directives 2018-05-11 17:30:28 +00:00