forked from OSchip/llvm-project
159 lines
5.0 KiB
YAML
159 lines
5.0 KiB
YAML
# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+sse2 -global-isel -run-pass=legalizer %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=NOT_AVX2 --check-prefix=SSE2
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# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx -global-isel -run-pass=legalizer %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=NOT_AVX2 --check-prefix=AVX1
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# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx2 -global-isel -run-pass=legalizer %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=AVX2
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--- |
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define void @test_add_v32i8() {
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%ret = add <32 x i8> undef, undef
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ret void
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}
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define void @test_add_v16i16() {
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%ret = add <16 x i16> undef, undef
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ret void
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}
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define void @test_add_v8i32() {
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%ret = add <8 x i32> undef, undef
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ret void
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}
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define void @test_add_v4i64() {
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%ret = add <4 x i64> undef, undef
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ret void
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}
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...
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---
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name: test_add_v32i8
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# ALL-LABEL: name: test_add_v32i8
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alignment: 4
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legalized: false
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regBankSelected: false
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registers:
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- { id: 0, class: _ }
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- { id: 1, class: _ }
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- { id: 2, class: _ }
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# NOT_AVX2: %0(<32 x s8>) = IMPLICIT_DEF
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# NOT_AVX2-NEXT: %1(<32 x s8>) = IMPLICIT_DEF
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# NOT_AVX2-NEXT: %3(<16 x s8>), %4(<16 x s8>) = G_UNMERGE_VALUES %0(<32 x s8>)
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# NOT_AVX2-NEXT: %5(<16 x s8>), %6(<16 x s8>) = G_UNMERGE_VALUES %1(<32 x s8>)
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# NOT_AVX2-NEXT: %7(<16 x s8>) = G_ADD %3, %5
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# NOT_AVX2-NEXT: %8(<16 x s8>) = G_ADD %4, %6
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# NOT_AVX2-NEXT: %2(<32 x s8>) = G_MERGE_VALUES %7(<16 x s8>), %8(<16 x s8>)
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# NOT_AVX2-NEXT: RET 0
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#
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# AVX2: %0(<32 x s8>) = IMPLICIT_DEF
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# AVX2-NEXT: %1(<32 x s8>) = IMPLICIT_DEF
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# AVX2-NEXT: %2(<32 x s8>) = G_ADD %0, %1
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# AVX2-NEXT: RET 0
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body: |
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bb.1 (%ir-block.0):
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liveins: %ymm0, %ymm1
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%0(<32 x s8>) = IMPLICIT_DEF
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%1(<32 x s8>) = IMPLICIT_DEF
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%2(<32 x s8>) = G_ADD %0, %1
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RET 0
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...
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---
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name: test_add_v16i16
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# ALL-LABEL: name: test_add_v16i16
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alignment: 4
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legalized: false
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regBankSelected: false
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registers:
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- { id: 0, class: _ }
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- { id: 1, class: _ }
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- { id: 2, class: _ }
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# NOT_AVX2: %0(<16 x s16>) = IMPLICIT_DEF
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# NOT_AVX2-NEXT: %1(<16 x s16>) = IMPLICIT_DEF
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# NOT_AVX2-NEXT: %3(<8 x s16>), %4(<8 x s16>) = G_UNMERGE_VALUES %0(<16 x s16>)
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# NOT_AVX2-NEXT: %5(<8 x s16>), %6(<8 x s16>) = G_UNMERGE_VALUES %1(<16 x s16>)
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# NOT_AVX2-NEXT: %7(<8 x s16>) = G_ADD %3, %5
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# NOT_AVX2-NEXT: %8(<8 x s16>) = G_ADD %4, %6
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# NOT_AVX2-NEXT: %2(<16 x s16>) = G_MERGE_VALUES %7(<8 x s16>), %8(<8 x s16>)
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# NOT_AVX2-NEXT: RET 0
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#
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# AVX2: %0(<16 x s16>) = IMPLICIT_DEF
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# AVX2-NEXT: %1(<16 x s16>) = IMPLICIT_DEF
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# AVX2-NEXT: %2(<16 x s16>) = G_ADD %0, %1
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# AVX2-NEXT: RET 0
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body: |
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bb.1 (%ir-block.0):
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liveins: %ymm0, %ymm1
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%0(<16 x s16>) = IMPLICIT_DEF
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%1(<16 x s16>) = IMPLICIT_DEF
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%2(<16 x s16>) = G_ADD %0, %1
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RET 0
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...
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---
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name: test_add_v8i32
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# ALL-LABEL: name: test_add_v8i32
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alignment: 4
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legalized: false
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regBankSelected: false
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registers:
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- { id: 0, class: _ }
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- { id: 1, class: _ }
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- { id: 2, class: _ }
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# NOT_AVX2: %0(<8 x s32>) = IMPLICIT_DEF
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# NOT_AVX2-NEXT: %1(<8 x s32>) = IMPLICIT_DEF
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# NOT_AVX2-NEXT: %3(<4 x s32>), %4(<4 x s32>) = G_UNMERGE_VALUES %0(<8 x s32>)
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# NOT_AVX2-NEXT: %5(<4 x s32>), %6(<4 x s32>) = G_UNMERGE_VALUES %1(<8 x s32>)
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# NOT_AVX2-NEXT: %7(<4 x s32>) = G_ADD %3, %5
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# NOT_AVX2-NEXT: %8(<4 x s32>) = G_ADD %4, %6
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# NOT_AVX2-NEXT: %2(<8 x s32>) = G_MERGE_VALUES %7(<4 x s32>), %8(<4 x s32>)
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# NOT_AVX2-NEXT: RET 0
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#
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# AVX2: %0(<8 x s32>) = IMPLICIT_DEF
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# AVX2-NEXT: %1(<8 x s32>) = IMPLICIT_DEF
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# AVX2-NEXT: %2(<8 x s32>) = G_ADD %0, %1
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# AVX2-NEXT: RET 0
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body: |
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bb.1 (%ir-block.0):
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liveins: %ymm0, %ymm1
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%0(<8 x s32>) = IMPLICIT_DEF
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%1(<8 x s32>) = IMPLICIT_DEF
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%2(<8 x s32>) = G_ADD %0, %1
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RET 0
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...
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---
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name: test_add_v4i64
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# ALL-LABEL: name: test_add_v4i64
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alignment: 4
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legalized: false
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regBankSelected: false
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registers:
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- { id: 0, class: _ }
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- { id: 1, class: _ }
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- { id: 2, class: _ }
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# NOT_AVX2: %0(<4 x s64>) = IMPLICIT_DEF
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# NOT_AVX2-NEXT: %1(<4 x s64>) = IMPLICIT_DEF
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# NOT_AVX2-NEXT: %3(<2 x s64>), %4(<2 x s64>) = G_UNMERGE_VALUES %0(<4 x s64>)
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# NOT_AVX2-NEXT: %5(<2 x s64>), %6(<2 x s64>) = G_UNMERGE_VALUES %1(<4 x s64>)
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# NOT_AVX2-NEXT: %7(<2 x s64>) = G_ADD %3, %5
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# NOT_AVX2-NEXT: %8(<2 x s64>) = G_ADD %4, %6
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# NOT_AVX2-NEXT: %2(<4 x s64>) = G_MERGE_VALUES %7(<2 x s64>), %8(<2 x s64>)
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# NOT_AVX2-NEXT: RET 0
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#
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# AVX2: %0(<4 x s64>) = IMPLICIT_DEF
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# AVX2-NEXT: %1(<4 x s64>) = IMPLICIT_DEF
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# AVX2-NEXT: %2(<4 x s64>) = G_ADD %0, %1
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# AVX2-NEXT: RET 0
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body: |
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bb.1 (%ir-block.0):
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liveins: %ymm0, %ymm1
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%0(<4 x s64>) = IMPLICIT_DEF
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%1(<4 x s64>) = IMPLICIT_DEF
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%2(<4 x s64>) = G_ADD %0, %1
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RET 0
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...
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