forked from OSchip/llvm-project
59 lines
2.4 KiB
LLVM
59 lines
2.4 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu -relocation-model=pic -post-RA-scheduler=1 -break-anti-dependencies=critical | FileCheck %s
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; PR20308 ( http://llvm.org/bugs/show_bug.cgi?id=20308 ).
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; The critical-anti-dependency-breaker must not use register def information from a kill inst.
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; This test case expects such an instruction to appear as a comment with def info for RDI.
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; There is an anti-dependency (WAR) hazard using RAX using default reg allocation and scheduling.
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; The post-RA-scheduler and critical-anti-dependency breaker can eliminate that hazard using R10.
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; That is the first free register that isn't used as a param in the call to "@Image".
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@PartClass = external global i32
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@NullToken = external global i64
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define i32 @Part_Create(i64* %Anchor, i32 %TypeNum, i32 %F, i32 %Z, i32* %Status, i64* %PartTkn) {
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; CHECK-LABEL: Part_Create:
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; CHECK: # %bb.0:
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; CHECK-NEXT: pushq %rbp
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; CHECK-NEXT: .cfi_def_cfa_offset 16
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; CHECK-NEXT: pushq %rbx
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; CHECK-NEXT: .cfi_def_cfa_offset 24
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; CHECK-NEXT: subq $24, %rsp
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; CHECK-NEXT: .cfi_def_cfa_offset 48
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; CHECK-NEXT: .cfi_offset %rbx, -24
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; CHECK-NEXT: .cfi_offset %rbp, -16
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; CHECK-NEXT: movq NullToken@{{.*}}(%rip), %rax
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; CHECK-NEXT: movq PartClass@{{.*}}(%rip), %r10
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; CHECK-NEXT: xorl %edx, %edx
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; CHECK-NEXT: xorl %ecx, %ecx
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; CHECK-NEXT: movq %rdi, %rbx
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; CHECK-NEXT: movq (%rax), %rax
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; CHECK-NEXT: movl (%r10), %ebp
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; CHECK-NEXT: movq %rax, {{[0-9]+}}(%rsp)
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; CHECK-NEXT: leaq {{[0-9]+}}(%rsp), %rax
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; CHECK-NEXT: movl %ebp, %esi
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; CHECK-NEXT: movq %rax, (%rsp)
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; CHECK-NEXT: callq Image@PLT
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; CHECK-NEXT: movq %rbx, %rdi
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; CHECK-NEXT: callq Create@PLT
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; CHECK-NEXT: movl %ebp, %eax
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; CHECK-NEXT: addq $24, %rsp
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; CHECK-NEXT: .cfi_def_cfa_offset 24
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; CHECK-NEXT: popq %rbx
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; CHECK-NEXT: .cfi_def_cfa_offset 16
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; CHECK-NEXT: popq %rbp
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; CHECK-NEXT: .cfi_def_cfa_offset 8
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; CHECK-NEXT: retq
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%PartObj = alloca i64*, align 8
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%Vchunk = alloca i64, align 8
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%1 = load i64, i64* @NullToken, align 4
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store i64 %1, i64* %Vchunk, align 8
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%2 = load i32, i32* @PartClass, align 4
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call i32 @Image(i64* %Anchor, i32 %2, i32 0, i32 0, i32* %Status, i64* %PartTkn, i64** %PartObj)
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call i32 @Create(i64* %Anchor)
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ret i32 %2
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}
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declare i32 @Image(i64*, i32, i32, i32, i32*, i64*, i64**)
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declare i32 @Create(i64*)
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