forked from OSchip/llvm-project
60 lines
1.7 KiB
LLVM
60 lines
1.7 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=i686-pc-win32 -mcpu=corei7 | FileCheck %s --check-prefix=X86
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; RUN: llc < %s -mtriple=x86_64-pc-win32 -mcpu=corei7 | FileCheck %s --check-prefix=X64
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define void @load_store(<4 x i16>* %in) {
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; X86-LABEL: load_store:
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; X86: # %bb.0: # %entry
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; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X86-NEXT: movq {{.*#+}} xmm0 = mem[0],zero
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; X86-NEXT: paddw %xmm0, %xmm0
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; X86-NEXT: movq %xmm0, (%eax)
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; X86-NEXT: retl
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;
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; X64-LABEL: load_store:
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; X64: # %bb.0: # %entry
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; X64-NEXT: movq {{.*#+}} xmm0 = mem[0],zero
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; X64-NEXT: paddw %xmm0, %xmm0
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; X64-NEXT: movq %xmm0, (%rcx)
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; X64-NEXT: retq
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entry:
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%A27 = load <4 x i16>, <4 x i16>* %in, align 4
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%A28 = add <4 x i16> %A27, %A27
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store <4 x i16> %A28, <4 x i16>* %in, align 4
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ret void
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}
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; Make sure that we store a 64bit value, even on 32bit systems.
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define void @store_64(<2 x i32>* %ptr) {
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; X86-LABEL: store_64:
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; X86: # %bb.0: # %BB
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; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X86-NEXT: xorps %xmm0, %xmm0
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; X86-NEXT: movlps %xmm0, (%eax)
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; X86-NEXT: retl
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;
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; X64-LABEL: store_64:
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; X64: # %bb.0: # %BB
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; X64-NEXT: movq $0, (%rcx)
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; X64-NEXT: retq
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BB:
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store <2 x i32> zeroinitializer, <2 x i32>* %ptr
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ret void
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}
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define <2 x i32> @load_64(<2 x i32>* %ptr) {
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; X86-LABEL: load_64:
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; X86: # %bb.0: # %BB
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; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X86-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
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; X86-NEXT: retl
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;
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; X64-LABEL: load_64:
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; X64: # %bb.0: # %BB
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; X64-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
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; X64-NEXT: retq
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BB:
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%t = load <2 x i32>, <2 x i32>* %ptr
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ret <2 x i32> %t
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}
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