forked from OSchip/llvm-project
52 lines
1.7 KiB
LLVM
52 lines
1.7 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=i386-apple-darwin | FileCheck %s
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; The inner loop should use [reg] addressing, not [reg+reg] addressing.
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; rdar://6403965
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target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
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target triple = "i386-apple-darwin9.5"
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define i8* @test(i8* %Q, i32* %L) nounwind {
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; CHECK-LABEL: test:
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; CHECK: ## %bb.0: ## %entry
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; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
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; CHECK-NEXT: jmp LBB0_2
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; CHECK-NEXT: .p2align 4, 0x90
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; CHECK-NEXT: LBB0_1: ## %bb
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; CHECK-NEXT: ## in Loop: Header=BB0_2 Depth=1
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; CHECK-NEXT: incl %eax
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; CHECK-NEXT: LBB0_2: ## %bb1
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; CHECK-NEXT: ## =>This Inner Loop Header: Depth=1
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; CHECK-NEXT: movzbl (%eax), %ecx
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; CHECK-NEXT: cmpb $12, %cl
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; CHECK-NEXT: je LBB0_1
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; CHECK-NEXT: ## %bb.3: ## %bb1
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; CHECK-NEXT: ## in Loop: Header=BB0_2 Depth=1
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; CHECK-NEXT: cmpb $42, %cl
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; CHECK-NEXT: je LBB0_1
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; CHECK-NEXT: ## %bb.4: ## %bb3
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; CHECK-NEXT: movb $4, 2(%eax)
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; CHECK-NEXT: retl
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entry:
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br label %bb1
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bb: ; preds = %bb1, %bb1
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%indvar.next = add i32 %P.0.rec, 1 ; <i32> [#uses=1]
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br label %bb1
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bb1: ; preds = %bb, %entry
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%P.0.rec = phi i32 [ 0, %entry ], [ %indvar.next, %bb ] ; <i32> [#uses=3]
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%P.0 = getelementptr i8, i8* %Q, i32 %P.0.rec ; <i8*> [#uses=2]
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%0 = load i8, i8* %P.0, align 1 ; <i8> [#uses=1]
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switch i8 %0, label %bb3 [
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i8 12, label %bb
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i8 42, label %bb
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]
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bb3: ; preds = %bb1
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%P.0.sum = add i32 %P.0.rec, 2 ; <i32> [#uses=1]
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%1 = getelementptr i8, i8* %Q, i32 %P.0.sum ; <i8*> [#uses=1]
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store i8 4, i8* %1, align 1
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ret i8* %P.0
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}
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