llvm-project/llvm/test/TableGen
Daniel Sanders f84bc3793e [globalisel] Update GlobalISel emitter to match new representation of extending loads
Summary:
Previously, a extending load was represented at (G_*EXT (G_LOAD x)).
This had a few drawbacks:
* G_LOAD had to be legal for all sizes you could extend from, even if
  registers didn't naturally hold those sizes.
* All sizes you could extend from had to be allocatable just in case the
  extend went missing (e.g. by optimization).
* At minimum, G_*EXT and G_TRUNC had to be legal for these sizes. As we
  improve optimization of extends and truncates, this legality requirement
  would spread without considerable care w.r.t when certain combines were
  permitted.
* The SelectionDAG importer required some ugly and fragile pattern
  rewriting to translate patterns into this style.

This patch changes the representation to:
* (G_[SZ]EXTLOAD x)
* (G_LOAD x) any-extends when MMO.getSize() * 8 < ResultTy.getSizeInBits()
which resolves these issues by allowing targets to work entirely in their
native register sizes, and by having a more direct translation from
SelectionDAG patterns.

Each extending load can be lowered by the legalizer into separate extends
and loads, however a target that supports s1 will need the any-extending
load to extend to at least s8 since LLVM does not represent memory accesses
smaller than 8 bit. The legalizer can widenScalar G_LOAD into an
any-extending load but sign/zero-extending loads need help from something
else like a combiner pass. A follow-up patch that adds combiner helpers for
for this will follow.

The new representation requires that the MMO correctly reflect the memory
access so this has been corrected in a couple tests. I've also moved the
extending loads to their own tests since they are (mostly) separate opcodes
now. Additionally, the re-write appears to have invalidated two tests from
select-with-no-legality-check.mir since the matcher table no longer contains
loads that result in s1's and they aren't legal in AArch64 anymore.

Depends on D45540

Reviewers: ab, aditya_nandakumar, bogner, rtereshin, volkan, rovka, javed.absar

Reviewed By: rtereshin

Subscribers: javed.absar, llvm-commits, kristof.beyls

Differential Revision: https://reviews.llvm.org/D45541

llvm-svn: 331601
2018-05-05 20:53:24 +00:00
..
2003-08-03-PassCode.td
2006-09-18-LargeInt.td
2010-03-24-PrematureDefaults.td
AllowDuplicateRegisterNames.td [TableGen] Give the option of tolerating duplicate register names 2017-12-07 09:51:55 +00:00
AnonDefinitionOnDemand.td TableGen: Delay instantiating inline anonymous records 2018-03-06 13:49:01 +00:00
AsmPredicateCondsEmission.td
AsmVariant.td [TableGen] Add a proper namespace to an Instruction in an AsmMatcher test. This is required after r307358. 2017-07-07 05:50:45 +00:00
BitOffsetDecoder.td TableGen: Explicitly check whether a record has been resolved 2018-03-06 13:48:47 +00:00
BitsInit.td TableGen: Allow !cast of records, cleanup conversion machinery 2018-03-06 13:48:39 +00:00
BitsInitOverflow.td TableGen: Explicitly check whether a record has been resolved 2018-03-06 13:48:47 +00:00
CStyleComment.td
ClassInstanceValue.td
ConcatenatedSubregs.td Address r311914 review comments 2017-08-28 20:11:27 +00:00
Dag.td
DefmInherit.td
DefmInsideMultiClass.td
DuplicateFieldValues.td [tablegen] Delete duplicates from a vector without skipping elements 2016-12-01 19:38:50 +00:00
FieldAccess.td TableGen: Allow !cast of records, cleanup conversion machinery 2018-03-06 13:48:39 +00:00
ForeachList.td TableGen: Allow arbitrary list values as ranges of foreach 2018-03-09 12:24:30 +00:00
ForeachLoop.td
ForwardRef.td
GeneralList.td
GlobalISelEmitter.td [globalisel] Update GlobalISel emitter to match new representation of extending loads 2018-05-05 20:53:24 +00:00
HwModeSelect.td TableGen support for parameterized register class information 2017-09-14 16:56:21 +00:00
Include.inc
Include.td
IntBitInit.td
LazyChange.td
LetInsideMultiClasses.td
ListArgs.td
ListArgsSimple.td
ListConversion.td
ListManip.td
ListOfList.td
ListSlices.td
LoLoL.td
MultiClass-defm-fail.td TableGen: Streamline how defs are instantiated 2018-03-21 17:12:53 +00:00
MultiClass-defm.td TableGen: Allow NAME in template arguments in defm in multiclass 2018-03-05 14:01:38 +00:00
MultiClass.td
MultiClassDefName.td
MultiClassInherit.td
MultiPat.td TableGen: Reimplement !foreach using the resolving mechanism 2018-03-05 15:21:04 +00:00
NestedForeach.td
Paste.td TableGen: Type-check BinOps 2018-03-14 11:00:43 +00:00
RegisterBankEmitter.td TableGen: Fix infinite recursion in RegisterBankEmitter 2017-01-30 15:07:01 +00:00
RegisterEncoder.td [TableGen] Add EncoderMethod to RegisterOperand 2017-05-15 10:13:07 +00:00
RelTest.td [mips] Improve diagnostics for instruction mapping 2018-01-08 16:25:40 +00:00
SetTheory.td
SiblingForeach.td
Slice.td
String.td
SuperSubclassSameName.td
TargetInstrInfo.td
TargetInstrSpec.td TableGen: Reimplement !foreach using the resolving mechanism 2018-03-05 15:21:04 +00:00
TemplateArgRename.td
Tree.td
TreeNames.td
TwoLevelName.td Add test cases that will show the bug that was fixed in r256725. 2016-01-13 07:53:11 +00:00
UnsetBitInit.td TableGen: Simplify BitsInit::resolveReferences 2018-03-06 13:48:30 +00:00
UnterminatedComment.td Make shell redirection construct portable 2017-07-12 13:24:46 +00:00
ValidIdentifiers.td
arithmetic.td TableGen: Type-check BinOps 2018-03-14 11:00:43 +00:00
cast-list-initializer.td
cast-typeerror.td TableGen: Check the dynamic type of !cast<Rec>(string) 2018-03-19 14:14:20 +00:00
cast.td
code.td TableGen: Allow !cast of records, cleanup conversion machinery 2018-03-06 13:48:39 +00:00
compare.td TableGen: Add !ne, !le, !lt, !ge, and !gt comparisons 2018-03-14 11:00:57 +00:00
dag-functional.td TableGen: Allow dag operators to be resolved late 2018-03-14 11:00:48 +00:00
defmclass.td
defset-typeerror.td TableGen: Add a defset statement 2018-03-09 12:24:42 +00:00
defset.td TableGen: Add a defset statement 2018-03-09 12:24:42 +00:00
eq.td TableGen: Add !ne, !le, !lt, !ge, and !gt comparisons 2018-03-14 11:00:57 +00:00
eqbit.td TableGen: Add !ne, !le, !lt, !ge, and !gt comparisons 2018-03-14 11:00:57 +00:00
foldl.td TableGen: Add !foldl operation 2018-03-06 13:49:16 +00:00
foreach-eval.td TableGen: Reimplement !foreach using the resolving mechanism 2018-03-05 15:21:04 +00:00
foreach-leak.td [TableGen] Don't quote variable name when printing !foreach. 2018-05-02 13:17:26 +00:00
foreach-multiclass.td TableGen: Streamline how defs are instantiated 2018-03-21 17:12:53 +00:00
foreach.td TableGen: Reimplement !foreach using the resolving mechanism 2018-03-05 15:21:04 +00:00
if-empty-list-arg.td
if-type.td TableGen: Generalize record types to fix typeIsConvertibleTo et al. 2018-03-06 13:48:20 +00:00
if.td TableGen: Generalize record types to fix typeIsConvertibleTo et al. 2018-03-06 13:48:20 +00:00
ifbit.td
intrinsic-long-name.td TableGen: Allow setting SDNodeProperties on intrinsics 2017-12-20 19:36:28 +00:00
intrinsic-struct.td TableGen: Allow setting SDNodeProperties on intrinsics 2017-12-20 19:36:28 +00:00
intrinsic-varargs.td TableGen: Allow setting SDNodeProperties on intrinsics 2017-12-20 19:36:28 +00:00
isa.td TableGen: add !isa operation 2018-03-09 12:24:06 +00:00
lisp.td
list-element-bitref.td
listconcat.td TableGen: Type-check BinOps 2018-03-14 11:00:43 +00:00
lit.local.cfg
math.td TableGen: Type-check BinOps 2018-03-14 11:00:43 +00:00
name-resolution-consistency.td TableGen: Streamline how defs are instantiated 2018-03-21 17:12:53 +00:00
nested-comment.td
pr8330.td
searchabletables-intrinsic.td TableGen: Support Intrinsic values in SearchableTable 2018-04-01 17:08:58 +00:00
self-reference-recursion.td TableGen: Explicitly forbid self-references to field members 2018-03-19 14:14:28 +00:00
self-reference-typeerror.td TableGen: Explicitly test some cases of self-references and !cast errors 2018-03-19 14:14:10 +00:00
self-reference.td TableGen: Streamline how defs are instantiated 2018-03-21 17:12:53 +00:00
size.td TableGen: Add !size operation 2018-02-23 10:46:07 +00:00
strconcat.td
subst.td
subst2.td
template-arg-dependency.td TableGen: Resolve all template args simultaneously in AddSubClass 2018-03-05 15:21:11 +00:00
trydecode-emission.td tests: accept different TargetOpcode values. 2016-07-07 17:51:42 +00:00
trydecode-emission2.td tests: accept different TargetOpcode values. 2016-07-07 17:51:42 +00:00
trydecode-emission3.td tests: accept different TargetOpcode values. 2016-07-07 17:51:42 +00:00
usevalname.td