forked from OSchip/llvm-project
535 lines
18 KiB
C++
535 lines
18 KiB
C++
//===- PatternMatchTest.cpp -----------------------------------------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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#include "llvm/CodeGen/GlobalISel/ConstantFoldingMIRBuilder.h"
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#include "llvm/CodeGen/GlobalISel/MIPatternMatch.h"
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#include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"
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#include "llvm/CodeGen/GlobalISel/Utils.h"
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#include "llvm/CodeGen/MIRParser/MIRParser.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineModuleInfo.h"
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#include "llvm/CodeGen/TargetFrameLowering.h"
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#include "llvm/CodeGen/TargetInstrInfo.h"
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#include "llvm/CodeGen/TargetLowering.h"
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#include "llvm/CodeGen/TargetSubtargetInfo.h"
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#include "llvm/Support/SourceMgr.h"
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#include "llvm/Support/TargetRegistry.h"
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#include "llvm/Support/TargetSelect.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/TargetOptions.h"
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#include "gtest/gtest.h"
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using namespace llvm;
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using namespace MIPatternMatch;
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namespace {
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void initLLVM() {
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InitializeAllTargets();
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InitializeAllTargetMCs();
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InitializeAllAsmPrinters();
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InitializeAllAsmParsers();
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PassRegistry *Registry = PassRegistry::getPassRegistry();
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initializeCore(*Registry);
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initializeCodeGen(*Registry);
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}
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/// Create a TargetMachine. As we lack a dedicated always available target for
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/// unittests, we go for "AArch64".
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std::unique_ptr<LLVMTargetMachine> createTargetMachine() {
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Triple TargetTriple("aarch64--");
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std::string Error;
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const Target *T = TargetRegistry::lookupTarget("", TargetTriple, Error);
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if (!T)
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return nullptr;
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TargetOptions Options;
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return std::unique_ptr<LLVMTargetMachine>(static_cast<LLVMTargetMachine*>(
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T->createTargetMachine("AArch64", "", "", Options, None, None,
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CodeGenOpt::Aggressive)));
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}
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std::unique_ptr<Module> parseMIR(LLVMContext &Context,
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std::unique_ptr<MIRParser> &MIR,
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const TargetMachine &TM, StringRef MIRCode,
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const char *FuncName, MachineModuleInfo &MMI) {
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SMDiagnostic Diagnostic;
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std::unique_ptr<MemoryBuffer> MBuffer = MemoryBuffer::getMemBuffer(MIRCode);
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MIR = createMIRParser(std::move(MBuffer), Context);
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if (!MIR)
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return nullptr;
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std::unique_ptr<Module> M = MIR->parseIRModule();
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if (!M)
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return nullptr;
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M->setDataLayout(TM.createDataLayout());
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if (MIR->parseMachineFunctions(*M, MMI))
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return nullptr;
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return M;
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}
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std::pair<std::unique_ptr<Module>, std::unique_ptr<MachineModuleInfo>>
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createDummyModule(LLVMContext &Context, const LLVMTargetMachine &TM,
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StringRef MIRFunc) {
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SmallString<512> S;
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StringRef MIRString = (Twine(R"MIR(
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---
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...
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name: func
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registers:
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- { id: 0, class: _ }
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- { id: 1, class: _ }
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- { id: 2, class: _ }
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- { id: 3, class: _ }
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body: |
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bb.1:
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%0(s64) = COPY $x0
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%1(s64) = COPY $x1
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%2(s64) = COPY $x2
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)MIR") + Twine(MIRFunc) + Twine("...\n"))
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.toNullTerminatedStringRef(S);
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std::unique_ptr<MIRParser> MIR;
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auto MMI = std::make_unique<MachineModuleInfo>(&TM);
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std::unique_ptr<Module> M =
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parseMIR(Context, MIR, TM, MIRString, "func", *MMI);
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return make_pair(std::move(M), std::move(MMI));
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}
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static MachineFunction *getMFFromMMI(const Module *M,
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const MachineModuleInfo *MMI) {
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Function *F = M->getFunction("func");
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auto *MF = MMI->getMachineFunction(*F);
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return MF;
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}
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static void collectCopies(SmallVectorImpl<Register> &Copies,
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MachineFunction *MF) {
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for (auto &MBB : *MF)
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for (MachineInstr &MI : MBB) {
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if (MI.getOpcode() == TargetOpcode::COPY)
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Copies.push_back(MI.getOperand(0).getReg());
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}
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}
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TEST(PatternMatchInstr, MatchIntConstant) {
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LLVMContext Context;
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std::unique_ptr<LLVMTargetMachine> TM = createTargetMachine();
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if (!TM)
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return;
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auto ModuleMMIPair = createDummyModule(Context, *TM, "");
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MachineFunction *MF =
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getMFFromMMI(ModuleMMIPair.first.get(), ModuleMMIPair.second.get());
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SmallVector<Register, 4> Copies;
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collectCopies(Copies, MF);
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MachineBasicBlock *EntryMBB = &*MF->begin();
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MachineIRBuilder B(*MF);
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MachineRegisterInfo &MRI = MF->getRegInfo();
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B.setInsertPt(*EntryMBB, EntryMBB->end());
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auto MIBCst = B.buildConstant(LLT::scalar(64), 42);
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int64_t Cst;
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bool match = mi_match(MIBCst->getOperand(0).getReg(), MRI, m_ICst(Cst));
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EXPECT_TRUE(match);
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EXPECT_EQ(Cst, 42);
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}
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TEST(PatternMatchInstr, MatchBinaryOp) {
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LLVMContext Context;
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std::unique_ptr<LLVMTargetMachine> TM = createTargetMachine();
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if (!TM)
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return;
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auto ModuleMMIPair = createDummyModule(Context, *TM, "");
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MachineFunction *MF =
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getMFFromMMI(ModuleMMIPair.first.get(), ModuleMMIPair.second.get());
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SmallVector<Register, 4> Copies;
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collectCopies(Copies, MF);
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MachineBasicBlock *EntryMBB = &*MF->begin();
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MachineIRBuilder B(*MF);
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MachineRegisterInfo &MRI = MF->getRegInfo();
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B.setInsertPt(*EntryMBB, EntryMBB->end());
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LLT s64 = LLT::scalar(64);
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auto MIBAdd = B.buildAdd(s64, Copies[0], Copies[1]);
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// Test case for no bind.
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bool match =
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mi_match(MIBAdd->getOperand(0).getReg(), MRI, m_GAdd(m_Reg(), m_Reg()));
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EXPECT_TRUE(match);
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Register Src0, Src1, Src2;
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match = mi_match(MIBAdd->getOperand(0).getReg(), MRI,
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m_GAdd(m_Reg(Src0), m_Reg(Src1)));
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EXPECT_TRUE(match);
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EXPECT_EQ(Src0, Copies[0]);
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EXPECT_EQ(Src1, Copies[1]);
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// Build MUL(ADD %0, %1), %2
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auto MIBMul = B.buildMul(s64, MIBAdd, Copies[2]);
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// Try to match MUL.
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match = mi_match(MIBMul->getOperand(0).getReg(), MRI,
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m_GMul(m_Reg(Src0), m_Reg(Src1)));
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EXPECT_TRUE(match);
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EXPECT_EQ(Src0, MIBAdd->getOperand(0).getReg());
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EXPECT_EQ(Src1, Copies[2]);
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// Try to match MUL(ADD)
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match = mi_match(MIBMul->getOperand(0).getReg(), MRI,
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m_GMul(m_GAdd(m_Reg(Src0), m_Reg(Src1)), m_Reg(Src2)));
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EXPECT_TRUE(match);
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EXPECT_EQ(Src0, Copies[0]);
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EXPECT_EQ(Src1, Copies[1]);
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EXPECT_EQ(Src2, Copies[2]);
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// Test Commutativity.
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auto MIBMul2 = B.buildMul(s64, Copies[0], B.buildConstant(s64, 42));
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// Try to match MUL(Cst, Reg) on src of MUL(Reg, Cst) to validate
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// commutativity.
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int64_t Cst;
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match = mi_match(MIBMul2->getOperand(0).getReg(), MRI,
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m_GMul(m_ICst(Cst), m_Reg(Src0)));
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EXPECT_TRUE(match);
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EXPECT_EQ(Cst, 42);
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EXPECT_EQ(Src0, Copies[0]);
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// Make sure commutative doesn't work with something like SUB.
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auto MIBSub = B.buildSub(s64, Copies[0], B.buildConstant(s64, 42));
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match = mi_match(MIBSub->getOperand(0).getReg(), MRI,
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m_GSub(m_ICst(Cst), m_Reg(Src0)));
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EXPECT_FALSE(match);
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auto MIBFMul = B.buildInstr(TargetOpcode::G_FMUL, {s64},
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{Copies[0], B.buildConstant(s64, 42)});
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// Match and test commutativity for FMUL.
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match = mi_match(MIBFMul->getOperand(0).getReg(), MRI,
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m_GFMul(m_ICst(Cst), m_Reg(Src0)));
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EXPECT_TRUE(match);
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EXPECT_EQ(Cst, 42);
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EXPECT_EQ(Src0, Copies[0]);
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// FSUB
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auto MIBFSub = B.buildInstr(TargetOpcode::G_FSUB, {s64},
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{Copies[0], B.buildConstant(s64, 42)});
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match = mi_match(MIBFSub->getOperand(0).getReg(), MRI,
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m_GFSub(m_Reg(Src0), m_Reg()));
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EXPECT_TRUE(match);
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EXPECT_EQ(Src0, Copies[0]);
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// Build AND %0, %1
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auto MIBAnd = B.buildAnd(s64, Copies[0], Copies[1]);
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// Try to match AND.
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match = mi_match(MIBAnd->getOperand(0).getReg(), MRI,
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m_GAnd(m_Reg(Src0), m_Reg(Src1)));
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EXPECT_TRUE(match);
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EXPECT_EQ(Src0, Copies[0]);
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EXPECT_EQ(Src1, Copies[1]);
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// Build OR %0, %1
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auto MIBOr = B.buildOr(s64, Copies[0], Copies[1]);
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// Try to match OR.
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match = mi_match(MIBOr->getOperand(0).getReg(), MRI,
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m_GOr(m_Reg(Src0), m_Reg(Src1)));
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EXPECT_TRUE(match);
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EXPECT_EQ(Src0, Copies[0]);
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EXPECT_EQ(Src1, Copies[1]);
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// Try to use the FoldableInstructionsBuilder to build binary ops.
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ConstantFoldingMIRBuilder CFB(B.getState());
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LLT s32 = LLT::scalar(32);
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auto MIBCAdd =
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CFB.buildAdd(s32, CFB.buildConstant(s32, 0), CFB.buildConstant(s32, 1));
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// This should be a constant now.
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match = mi_match(MIBCAdd->getOperand(0).getReg(), MRI, m_ICst(Cst));
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EXPECT_TRUE(match);
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EXPECT_EQ(Cst, 1);
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auto MIBCAdd1 =
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CFB.buildInstr(TargetOpcode::G_ADD, {s32},
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{CFB.buildConstant(s32, 0), CFB.buildConstant(s32, 1)});
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// This should be a constant now.
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match = mi_match(MIBCAdd1->getOperand(0).getReg(), MRI, m_ICst(Cst));
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EXPECT_TRUE(match);
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EXPECT_EQ(Cst, 1);
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// Try one of the other constructors of MachineIRBuilder to make sure it's
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// compatible.
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ConstantFoldingMIRBuilder CFB1(*MF);
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CFB1.setInsertPt(*EntryMBB, EntryMBB->end());
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auto MIBCSub =
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CFB1.buildInstr(TargetOpcode::G_SUB, {s32},
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{CFB1.buildConstant(s32, 1), CFB1.buildConstant(s32, 1)});
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// This should be a constant now.
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match = mi_match(MIBCSub->getOperand(0).getReg(), MRI, m_ICst(Cst));
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EXPECT_TRUE(match);
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EXPECT_EQ(Cst, 0);
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auto MIBCSext1 =
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CFB1.buildInstr(TargetOpcode::G_SEXT_INREG, {s32},
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{CFB1.buildConstant(s32, 0x01), uint64_t(8)});
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// This should be a constant now.
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match = mi_match(MIBCSext1->getOperand(0).getReg(), MRI, m_ICst(Cst));
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EXPECT_TRUE(match);
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EXPECT_EQ(1, Cst);
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auto MIBCSext2 =
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CFB1.buildInstr(TargetOpcode::G_SEXT_INREG, {s32},
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{CFB1.buildConstant(s32, 0x80), uint64_t(8)});
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// This should be a constant now.
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match = mi_match(MIBCSext2->getOperand(0).getReg(), MRI, m_ICst(Cst));
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EXPECT_TRUE(match);
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EXPECT_EQ(-0x80, Cst);
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}
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TEST(PatternMatchInstr, MatchFPUnaryOp) {
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LLVMContext Context;
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std::unique_ptr<LLVMTargetMachine> TM = createTargetMachine();
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if (!TM)
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return;
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auto ModuleMMIPair = createDummyModule(Context, *TM, "");
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MachineFunction *MF =
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getMFFromMMI(ModuleMMIPair.first.get(), ModuleMMIPair.second.get());
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SmallVector<Register, 4> Copies;
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collectCopies(Copies, MF);
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MachineBasicBlock *EntryMBB = &*MF->begin();
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MachineIRBuilder B(*MF);
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MachineRegisterInfo &MRI = MF->getRegInfo();
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B.setInsertPt(*EntryMBB, EntryMBB->end());
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// Truncate s64 to s32.
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LLT s32 = LLT::scalar(32);
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auto Copy0s32 = B.buildFPTrunc(s32, Copies[0]);
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// Match G_FABS.
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auto MIBFabs = B.buildInstr(TargetOpcode::G_FABS, {s32}, {Copy0s32});
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bool match = mi_match(MIBFabs->getOperand(0).getReg(), MRI, m_GFabs(m_Reg()));
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EXPECT_TRUE(match);
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Register Src;
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auto MIBFNeg = B.buildInstr(TargetOpcode::G_FNEG, {s32}, {Copy0s32});
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match = mi_match(MIBFNeg->getOperand(0).getReg(), MRI, m_GFNeg(m_Reg(Src)));
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EXPECT_TRUE(match);
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EXPECT_EQ(Src, Copy0s32->getOperand(0).getReg());
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match = mi_match(MIBFabs->getOperand(0).getReg(), MRI, m_GFabs(m_Reg(Src)));
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EXPECT_TRUE(match);
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EXPECT_EQ(Src, Copy0s32->getOperand(0).getReg());
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// Build and match FConstant.
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auto MIBFCst = B.buildFConstant(s32, .5);
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const ConstantFP *TmpFP{};
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match = mi_match(MIBFCst->getOperand(0).getReg(), MRI, m_GFCst(TmpFP));
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EXPECT_TRUE(match);
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EXPECT_TRUE(TmpFP);
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APFloat APF((float).5);
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auto *CFP = ConstantFP::get(Context, APF);
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EXPECT_EQ(CFP, TmpFP);
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// Build double float.
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LLT s64 = LLT::scalar(64);
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auto MIBFCst64 = B.buildFConstant(s64, .5);
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const ConstantFP *TmpFP64{};
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match = mi_match(MIBFCst64->getOperand(0).getReg(), MRI, m_GFCst(TmpFP64));
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EXPECT_TRUE(match);
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EXPECT_TRUE(TmpFP64);
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APFloat APF64(.5);
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auto CFP64 = ConstantFP::get(Context, APF64);
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EXPECT_EQ(CFP64, TmpFP64);
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EXPECT_NE(TmpFP64, TmpFP);
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// Build half float.
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LLT s16 = LLT::scalar(16);
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auto MIBFCst16 = B.buildFConstant(s16, .5);
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const ConstantFP *TmpFP16{};
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match = mi_match(MIBFCst16->getOperand(0).getReg(), MRI, m_GFCst(TmpFP16));
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EXPECT_TRUE(match);
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EXPECT_TRUE(TmpFP16);
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bool Ignored;
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APFloat APF16(.5);
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APF16.convert(APFloat::IEEEhalf(), APFloat::rmNearestTiesToEven, &Ignored);
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auto CFP16 = ConstantFP::get(Context, APF16);
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EXPECT_EQ(TmpFP16, CFP16);
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EXPECT_NE(TmpFP16, TmpFP);
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}
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TEST(PatternMatchInstr, MatchExtendsTrunc) {
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LLVMContext Context;
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std::unique_ptr<LLVMTargetMachine> TM = createTargetMachine();
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if (!TM)
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return;
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auto ModuleMMIPair = createDummyModule(Context, *TM, "");
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MachineFunction *MF =
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getMFFromMMI(ModuleMMIPair.first.get(), ModuleMMIPair.second.get());
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SmallVector<Register, 4> Copies;
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collectCopies(Copies, MF);
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MachineBasicBlock *EntryMBB = &*MF->begin();
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MachineIRBuilder B(*MF);
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MachineRegisterInfo &MRI = MF->getRegInfo();
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B.setInsertPt(*EntryMBB, EntryMBB->end());
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LLT s64 = LLT::scalar(64);
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LLT s32 = LLT::scalar(32);
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auto MIBTrunc = B.buildTrunc(s32, Copies[0]);
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auto MIBAExt = B.buildAnyExt(s64, MIBTrunc);
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auto MIBZExt = B.buildZExt(s64, MIBTrunc);
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auto MIBSExt = B.buildSExt(s64, MIBTrunc);
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Register Src0;
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bool match =
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mi_match(MIBTrunc->getOperand(0).getReg(), MRI, m_GTrunc(m_Reg(Src0)));
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EXPECT_TRUE(match);
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EXPECT_EQ(Src0, Copies[0]);
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match =
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mi_match(MIBAExt->getOperand(0).getReg(), MRI, m_GAnyExt(m_Reg(Src0)));
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EXPECT_TRUE(match);
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EXPECT_EQ(Src0, MIBTrunc->getOperand(0).getReg());
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match = mi_match(MIBSExt->getOperand(0).getReg(), MRI, m_GSExt(m_Reg(Src0)));
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EXPECT_TRUE(match);
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EXPECT_EQ(Src0, MIBTrunc->getOperand(0).getReg());
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match = mi_match(MIBZExt->getOperand(0).getReg(), MRI, m_GZExt(m_Reg(Src0)));
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EXPECT_TRUE(match);
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EXPECT_EQ(Src0, MIBTrunc->getOperand(0).getReg());
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// Match ext(trunc src)
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match = mi_match(MIBAExt->getOperand(0).getReg(), MRI,
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m_GAnyExt(m_GTrunc(m_Reg(Src0))));
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EXPECT_TRUE(match);
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EXPECT_EQ(Src0, Copies[0]);
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match = mi_match(MIBSExt->getOperand(0).getReg(), MRI,
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m_GSExt(m_GTrunc(m_Reg(Src0))));
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EXPECT_TRUE(match);
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EXPECT_EQ(Src0, Copies[0]);
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match = mi_match(MIBZExt->getOperand(0).getReg(), MRI,
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m_GZExt(m_GTrunc(m_Reg(Src0))));
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EXPECT_TRUE(match);
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EXPECT_EQ(Src0, Copies[0]);
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}
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TEST(PatternMatchInstr, MatchSpecificType) {
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LLVMContext Context;
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std::unique_ptr<LLVMTargetMachine> TM = createTargetMachine();
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if (!TM)
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return;
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auto ModuleMMIPair = createDummyModule(Context, *TM, "");
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MachineFunction *MF =
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getMFFromMMI(ModuleMMIPair.first.get(), ModuleMMIPair.second.get());
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SmallVector<Register, 4> Copies;
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collectCopies(Copies, MF);
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MachineBasicBlock *EntryMBB = &*MF->begin();
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MachineIRBuilder B(*MF);
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MachineRegisterInfo &MRI = MF->getRegInfo();
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|
B.setInsertPt(*EntryMBB, EntryMBB->end());
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|
|
|
// Try to match a 64bit add.
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|
LLT s64 = LLT::scalar(64);
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|
LLT s32 = LLT::scalar(32);
|
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auto MIBAdd = B.buildAdd(s64, Copies[0], Copies[1]);
|
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EXPECT_FALSE(mi_match(MIBAdd->getOperand(0).getReg(), MRI,
|
|
m_GAdd(m_SpecificType(s32), m_Reg())));
|
|
EXPECT_TRUE(mi_match(MIBAdd->getOperand(0).getReg(), MRI,
|
|
m_GAdd(m_SpecificType(s64), m_Reg())));
|
|
|
|
// Try to match the destination type of a bitcast.
|
|
LLT v2s32 = LLT::vector(2, 32);
|
|
auto MIBCast = B.buildCast(v2s32, Copies[0]);
|
|
EXPECT_TRUE(
|
|
mi_match(MIBCast->getOperand(0).getReg(), MRI, m_GBitcast(m_Reg())));
|
|
EXPECT_TRUE(
|
|
mi_match(MIBCast->getOperand(0).getReg(), MRI, m_SpecificType(v2s32)));
|
|
EXPECT_TRUE(
|
|
mi_match(MIBCast->getOperand(1).getReg(), MRI, m_SpecificType(s64)));
|
|
|
|
// Build a PTRToInt and INTTOPTR and match and test them.
|
|
LLT PtrTy = LLT::pointer(0, 64);
|
|
auto MIBIntToPtr = B.buildCast(PtrTy, Copies[0]);
|
|
auto MIBPtrToInt = B.buildCast(s64, MIBIntToPtr);
|
|
Register Src0;
|
|
|
|
// match the ptrtoint(inttoptr reg)
|
|
bool match = mi_match(MIBPtrToInt->getOperand(0).getReg(), MRI,
|
|
m_GPtrToInt(m_GIntToPtr(m_Reg(Src0))));
|
|
EXPECT_TRUE(match);
|
|
EXPECT_EQ(Src0, Copies[0]);
|
|
}
|
|
|
|
TEST(PatternMatchInstr, MatchCombinators) {
|
|
LLVMContext Context;
|
|
std::unique_ptr<LLVMTargetMachine> TM = createTargetMachine();
|
|
if (!TM)
|
|
return;
|
|
auto ModuleMMIPair = createDummyModule(Context, *TM, "");
|
|
MachineFunction *MF =
|
|
getMFFromMMI(ModuleMMIPair.first.get(), ModuleMMIPair.second.get());
|
|
SmallVector<Register, 4> Copies;
|
|
collectCopies(Copies, MF);
|
|
MachineBasicBlock *EntryMBB = &*MF->begin();
|
|
MachineIRBuilder B(*MF);
|
|
MachineRegisterInfo &MRI = MF->getRegInfo();
|
|
B.setInsertPt(*EntryMBB, EntryMBB->end());
|
|
LLT s64 = LLT::scalar(64);
|
|
LLT s32 = LLT::scalar(32);
|
|
auto MIBAdd = B.buildAdd(s64, Copies[0], Copies[1]);
|
|
Register Src0, Src1;
|
|
bool match =
|
|
mi_match(MIBAdd->getOperand(0).getReg(), MRI,
|
|
m_all_of(m_SpecificType(s64), m_GAdd(m_Reg(Src0), m_Reg(Src1))));
|
|
EXPECT_TRUE(match);
|
|
EXPECT_EQ(Src0, Copies[0]);
|
|
EXPECT_EQ(Src1, Copies[1]);
|
|
// Check for s32 (which should fail).
|
|
match =
|
|
mi_match(MIBAdd->getOperand(0).getReg(), MRI,
|
|
m_all_of(m_SpecificType(s32), m_GAdd(m_Reg(Src0), m_Reg(Src1))));
|
|
EXPECT_FALSE(match);
|
|
match =
|
|
mi_match(MIBAdd->getOperand(0).getReg(), MRI,
|
|
m_any_of(m_SpecificType(s32), m_GAdd(m_Reg(Src0), m_Reg(Src1))));
|
|
EXPECT_TRUE(match);
|
|
EXPECT_EQ(Src0, Copies[0]);
|
|
EXPECT_EQ(Src1, Copies[1]);
|
|
|
|
// Match a case where none of the predicates hold true.
|
|
match = mi_match(
|
|
MIBAdd->getOperand(0).getReg(), MRI,
|
|
m_any_of(m_SpecificType(LLT::scalar(16)), m_GSub(m_Reg(), m_Reg())));
|
|
EXPECT_FALSE(match);
|
|
}
|
|
|
|
TEST(PatternMatchInstr, MatchMiscellaneous) {
|
|
LLVMContext Context;
|
|
std::unique_ptr<LLVMTargetMachine> TM = createTargetMachine();
|
|
if (!TM)
|
|
return;
|
|
auto ModuleMMIPair = createDummyModule(Context, *TM, "");
|
|
MachineFunction *MF =
|
|
getMFFromMMI(ModuleMMIPair.first.get(), ModuleMMIPair.second.get());
|
|
SmallVector<Register, 4> Copies;
|
|
collectCopies(Copies, MF);
|
|
MachineBasicBlock *EntryMBB = &*MF->begin();
|
|
MachineIRBuilder B(*MF);
|
|
MachineRegisterInfo &MRI = MF->getRegInfo();
|
|
B.setInsertPt(*EntryMBB, EntryMBB->end());
|
|
LLT s64 = LLT::scalar(64);
|
|
auto MIBAdd = B.buildAdd(s64, Copies[0], Copies[1]);
|
|
// Make multiple uses of this add.
|
|
B.buildCast(LLT::pointer(0, 32), MIBAdd);
|
|
B.buildCast(LLT::pointer(1, 32), MIBAdd);
|
|
bool match = mi_match(MIBAdd.getReg(0), MRI, m_GAdd(m_Reg(), m_Reg()));
|
|
EXPECT_TRUE(match);
|
|
match = mi_match(MIBAdd.getReg(0), MRI, m_OneUse(m_GAdd(m_Reg(), m_Reg())));
|
|
EXPECT_FALSE(match);
|
|
}
|
|
} // namespace
|
|
|
|
int main(int argc, char **argv) {
|
|
::testing::InitGoogleTest(&argc, argv);
|
|
initLLVM();
|
|
return RUN_ALL_TESTS();
|
|
}
|