forked from OSchip/llvm-project
89 lines
2.6 KiB
YAML
89 lines
2.6 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -run-pass=peephole-opt -mtriple=x86_64-- %s -o - | FileCheck %s
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--- |
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target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
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target triple = "x86_64-unknown-linux-gnu"
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define i32 @atomic(i8** %arg) {
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%load = load atomic i8*, i8** %arg unordered, align 8
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%cmp = icmp eq i8* %load, null
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%zext = zext i1 %cmp to i32
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ret i32 %zext
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}
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define i32 @nonatomic_unoptimized(i8** %arg) {
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%load = load i8*, i8** %arg, align 8
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%cmp = icmp eq i8* %load, null
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%zext = zext i1 %cmp to i32
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ret i32 %zext
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}
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...
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---
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name: atomic
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alignment: 16
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tracksRegLiveness: true
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registers:
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- { id: 0, class: gr64 }
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- { id: 1, class: gr64 }
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- { id: 2, class: gr8 }
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- { id: 3, class: gr32 }
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liveins:
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- { reg: '$rdi', virtual-reg: '%0' }
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machineFunctionInfo: {}
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body: |
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bb.0 (%ir-block.0):
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liveins: $rdi
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; CHECK-LABEL: name: atomic
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; CHECK: liveins: $rdi
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; CHECK: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
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; CHECK: CMP64mi8 [[COPY]], 1, $noreg, 0, $noreg, 0, implicit-def $eflags :: (load unordered 8 from %ir.arg)
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; CHECK: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 4, implicit $eflags
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; CHECK: [[MOVZX32rr8_:%[0-9]+]]:gr32 = MOVZX32rr8 killed [[SETCCr]]
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; CHECK: $eax = COPY [[MOVZX32rr8_]]
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; CHECK: RET 0, $eax
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%0:gr64 = COPY $rdi
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%1:gr64 = MOV64rm %0, 1, $noreg, 0, $noreg :: (load unordered 8 from %ir.arg)
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TEST64rr %1, %1, implicit-def $eflags
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%2:gr8 = SETCCr 4, implicit $eflags
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%3:gr32 = MOVZX32rr8 killed %2
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$eax = COPY %3
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RET 0, $eax
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...
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---
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name: nonatomic_unoptimized
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alignment: 16
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tracksRegLiveness: true
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registers:
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- { id: 0, class: gr64 }
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- { id: 1, class: gr64 }
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- { id: 2, class: gr8 }
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- { id: 3, class: gr32 }
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liveins:
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- { reg: '$rdi', virtual-reg: '%0' }
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machineFunctionInfo: {}
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body: |
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bb.0 (%ir-block.0):
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liveins: $rdi
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; CHECK-LABEL: name: nonatomic_unoptimized
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; CHECK: liveins: $rdi
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; CHECK: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
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; CHECK: CMP64mi8 [[COPY]], 1, $noreg, 0, $noreg, 0, implicit-def $eflags :: (load 8 from %ir.arg)
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; CHECK: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 4, implicit $eflags
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; CHECK: [[MOVZX32rr8_:%[0-9]+]]:gr32 = MOVZX32rr8 killed [[SETCCr]]
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; CHECK: $eax = COPY [[MOVZX32rr8_]]
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; CHECK: RET 0, $eax
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%0:gr64 = COPY $rdi
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%1:gr64 = MOV64rm %0, 1, $noreg, 0, $noreg :: (load 8 from %ir.arg)
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TEST64rr %1, %1, implicit-def $eflags
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%2:gr8 = SETCCr 4, implicit $eflags
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%3:gr32 = MOVZX32rr8 killed %2
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$eax = COPY %3
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RET 0, $eax
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...
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