forked from OSchip/llvm-project
132 lines
3.6 KiB
YAML
132 lines
3.6 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=x86_64-linux-gnu -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL
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--- |
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define <64 x i8> @test_sub_v64i8(<64 x i8> %arg1, <64 x i8> %arg2) #0 {
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%ret = sub <64 x i8> %arg1, %arg2
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ret <64 x i8> %ret
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}
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define <32 x i16> @test_sub_v32i16(<32 x i16> %arg1, <32 x i16> %arg2) #0 {
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%ret = sub <32 x i16> %arg1, %arg2
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ret <32 x i16> %ret
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}
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define <16 x i32> @test_sub_v16i32(<16 x i32> %arg1, <16 x i32> %arg2) #1 {
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%ret = sub <16 x i32> %arg1, %arg2
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ret <16 x i32> %ret
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}
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define <8 x i64> @test_sub_v8i64(<8 x i64> %arg1, <8 x i64> %arg2) #1 {
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%ret = sub <8 x i64> %arg1, %arg2
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ret <8 x i64> %ret
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}
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attributes #0 = { "target-features"="+avx512f,+avx512bw" }
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attributes #1 = { "target-features"="+avx512f" }
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...
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---
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name: test_sub_v64i8
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alignment: 16
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legalized: true
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regBankSelected: true
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registers:
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- { id: 0, class: vecr }
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- { id: 1, class: vecr }
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- { id: 2, class: vecr }
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body: |
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bb.1 (%ir-block.0):
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liveins: $zmm0, $zmm1
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; ALL-LABEL: name: test_sub_v64i8
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; ALL: [[COPY:%[0-9]+]]:vr512 = COPY $zmm0
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; ALL: [[COPY1:%[0-9]+]]:vr512 = COPY $zmm1
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; ALL: [[VPSUBBZrr:%[0-9]+]]:vr512 = VPSUBBZrr [[COPY]], [[COPY1]]
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; ALL: $zmm0 = COPY [[VPSUBBZrr]]
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; ALL: RET 0, implicit $zmm0
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%0(<64 x s8>) = COPY $zmm0
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%1(<64 x s8>) = COPY $zmm1
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%2(<64 x s8>) = G_SUB %0, %1
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$zmm0 = COPY %2(<64 x s8>)
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RET 0, implicit $zmm0
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...
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---
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name: test_sub_v32i16
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alignment: 16
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legalized: true
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regBankSelected: true
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registers:
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- { id: 0, class: vecr }
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- { id: 1, class: vecr }
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- { id: 2, class: vecr }
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body: |
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bb.1 (%ir-block.0):
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liveins: $zmm0, $zmm1
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; ALL-LABEL: name: test_sub_v32i16
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; ALL: [[COPY:%[0-9]+]]:vr512 = COPY $zmm0
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; ALL: [[COPY1:%[0-9]+]]:vr512 = COPY $zmm1
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; ALL: [[VPSUBWZrr:%[0-9]+]]:vr512 = VPSUBWZrr [[COPY]], [[COPY1]]
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; ALL: $zmm0 = COPY [[VPSUBWZrr]]
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; ALL: RET 0, implicit $zmm0
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%0(<32 x s16>) = COPY $zmm0
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%1(<32 x s16>) = COPY $zmm1
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%2(<32 x s16>) = G_SUB %0, %1
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$zmm0 = COPY %2(<32 x s16>)
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RET 0, implicit $zmm0
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...
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---
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name: test_sub_v16i32
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alignment: 16
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legalized: true
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regBankSelected: true
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registers:
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- { id: 0, class: vecr }
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- { id: 1, class: vecr }
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- { id: 2, class: vecr }
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body: |
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bb.1 (%ir-block.0):
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liveins: $zmm0, $zmm1
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; ALL-LABEL: name: test_sub_v16i32
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; ALL: [[COPY:%[0-9]+]]:vr512 = COPY $zmm0
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; ALL: [[COPY1:%[0-9]+]]:vr512 = COPY $zmm1
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; ALL: [[VPSUBDZrr:%[0-9]+]]:vr512 = VPSUBDZrr [[COPY]], [[COPY1]]
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; ALL: $zmm0 = COPY [[VPSUBDZrr]]
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; ALL: RET 0, implicit $zmm0
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%0(<16 x s32>) = COPY $zmm0
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%1(<16 x s32>) = COPY $zmm1
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%2(<16 x s32>) = G_SUB %0, %1
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$zmm0 = COPY %2(<16 x s32>)
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RET 0, implicit $zmm0
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...
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---
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name: test_sub_v8i64
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alignment: 16
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legalized: true
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regBankSelected: true
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registers:
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- { id: 0, class: vecr }
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- { id: 1, class: vecr }
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- { id: 2, class: vecr }
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body: |
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bb.1 (%ir-block.0):
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liveins: $zmm0, $zmm1
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; ALL-LABEL: name: test_sub_v8i64
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; ALL: [[COPY:%[0-9]+]]:vr512 = COPY $zmm0
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; ALL: [[COPY1:%[0-9]+]]:vr512 = COPY $zmm1
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; ALL: [[VPSUBQZrr:%[0-9]+]]:vr512 = VPSUBQZrr [[COPY]], [[COPY1]]
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; ALL: $zmm0 = COPY [[VPSUBQZrr]]
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; ALL: RET 0, implicit $zmm0
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%0(<8 x s64>) = COPY $zmm0
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%1(<8 x s64>) = COPY $zmm1
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%2(<8 x s64>) = G_SUB %0, %1
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$zmm0 = COPY %2(<8 x s64>)
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RET 0, implicit $zmm0
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...
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