forked from OSchip/llvm-project
47 lines
2.4 KiB
LLVM
47 lines
2.4 KiB
LLVM
; RUN: llc -march=hexagon -hexagon-initial-cfg-cleanup=0 < %s | FileCheck %s
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; CHECK: = vmem(r{{[0-9]+}}++#1)
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target triple = "hexagon-unknown--elf"
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declare <32 x i32> @llvm.hexagon.V6.hi.128B(<64 x i32>) #0
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declare <64 x i32> @llvm.hexagon.V6.vcombine.128B(<32 x i32>, <32 x i32>) #0
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declare <64 x i32> @llvm.hexagon.V6.vzb.128B(<32 x i32>) #0
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declare <32 x i32> @llvm.hexagon.V6.vsathub.128B(<32 x i32>, <32 x i32>) #0
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declare <64 x i32> @llvm.hexagon.V6.vaddh.dv.128B(<64 x i32>, <64 x i32>) #0
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declare <64 x i32> @llvm.hexagon.V6.vadduhsat.dv.128B(<64 x i32>, <64 x i32>) #0
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declare <32 x i32> @llvm.hexagon.V6.vabsdiffuh.128B(<32 x i32>, <32 x i32>) #0
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define void @f0(i8* %a0, <32 x i32>* %a1) #1 {
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b0:
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br label %b1
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b1: ; preds = %b2, %b1
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%v0 = phi <128 x i8> [ %v7, %b1 ], [ undef, %b0 ]
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%v1 = phi i32 [ %v19, %b1 ], [ 0, %b0 ]
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%v2 = add nsw i32 %v1, undef
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%v3 = shl i32 %v2, 7
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%v4 = add nsw i32 %v3, 128
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%v5 = getelementptr inbounds i8, i8* %a0, i32 %v4
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%v6 = bitcast i8* %v5 to <128 x i8>*
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%v7 = load <128 x i8>, <128 x i8>* %v6, align 128
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%v8 = bitcast <128 x i8> %v0 to <32 x i32>
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%v9 = tail call <32 x i32> @llvm.hexagon.V6.valignbi.128B(<32 x i32> undef, <32 x i32> %v8, i32 1)
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%v10 = tail call <64 x i32> @llvm.hexagon.V6.vzb.128B(<32 x i32> %v9) #1
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%v11 = tail call <64 x i32> @llvm.hexagon.V6.vadduhsat.dv.128B(<64 x i32> undef, <64 x i32> %v10) #1
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%v12 = tail call <64 x i32> @llvm.hexagon.V6.vadduhsat.dv.128B(<64 x i32> %v11, <64 x i32> undef) #1
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%v13 = tail call <32 x i32> @llvm.hexagon.V6.hi.128B(<64 x i32> %v12)
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%v14 = tail call <32 x i32> @llvm.hexagon.V6.vabsdiffuh.128B(<32 x i32> undef, <32 x i32> %v13) #1
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%v15 = tail call <64 x i32> @llvm.hexagon.V6.vcombine.128B(<32 x i32> %v14, <32 x i32> undef)
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%v16 = tail call <64 x i32> @llvm.hexagon.V6.vaddh.dv.128B(<64 x i32> undef, <64 x i32> %v15) #1
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%v17 = tail call <32 x i32> @llvm.hexagon.V6.hi.128B(<64 x i32> %v16) #1
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%v18 = tail call <32 x i32> @llvm.hexagon.V6.vsathub.128B(<32 x i32> %v17, <32 x i32> undef) #1
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store <32 x i32> %v18, <32 x i32>* %a1, align 128
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%v19 = add nuw nsw i32 %v1, 1
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br label %b1
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}
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declare <32 x i32> @llvm.hexagon.V6.valignbi.128B(<32 x i32>, <32 x i32>, i32) #0
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attributes #0 = { nounwind readnone }
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attributes #1 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length128b" }
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