forked from OSchip/llvm-project
355 lines
10 KiB
LLVM
355 lines
10 KiB
LLVM
; RUN: llc < %s -mtriple=aarch64-eabi -mattr=+v8.2a,+fullfp16 | FileCheck %s
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declare half @llvm.aarch64.sisd.fabd.f16(half, half)
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declare half @llvm.aarch64.neon.fmax.f16(half, half)
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declare half @llvm.aarch64.neon.fmin.f16(half, half)
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declare half @llvm.aarch64.neon.frsqrts.f16(half, half)
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declare half @llvm.aarch64.neon.frecps.f16(half, half)
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declare half @llvm.aarch64.neon.fmulx.f16(half, half)
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declare half @llvm.fabs.f16(half)
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declare i32 @llvm.aarch64.neon.facge.i32.f16(half, half)
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declare i32 @llvm.aarch64.neon.facgt.i32.f16(half, half)
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define dso_local half @t_vabdh_f16(half %a, half %b) {
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; CHECK-LABEL: t_vabdh_f16:
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; CHECK: fabd h0, h0, h1
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; CHECK-NEXT: ret
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entry:
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%vabdh_f16 = tail call half @llvm.aarch64.sisd.fabd.f16(half %a, half %b)
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ret half %vabdh_f16
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}
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define dso_local half @t_vabdh_f16_from_fsub_fabs(half %a, half %b) {
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; CHECK-LABEL: t_vabdh_f16_from_fsub_fabs:
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; CHECK: fabd h0, h0, h1
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; CHECK-NEXT: ret
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entry:
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%sub = fsub half %a, %b
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%abs = tail call half @llvm.fabs.f16(half %sub)
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ret half %abs
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}
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define dso_local i16 @t_vceqh_f16(half %a, half %b) {
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; CHECK-LABEL: t_vceqh_f16:
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; CHECK: fcmp h0, h1
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; CHECK-NEXT: csetm w0, eq
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; CHECK-NEXT: ret
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entry:
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%0 = fcmp oeq half %a, %b
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%vcmpd = sext i1 %0 to i16
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ret i16 %vcmpd
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}
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define dso_local i16 @t_vcgeh_f16(half %a, half %b) {
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; CHECK-LABEL: t_vcgeh_f16:
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; CHECK: fcmp h0, h1
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; CHECK-NEXT: csetm w0, ge
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; CHECK-NEXT: ret
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entry:
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%0 = fcmp oge half %a, %b
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%vcmpd = sext i1 %0 to i16
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ret i16 %vcmpd
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}
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define dso_local i16 @t_vcgth_f16(half %a, half %b) {
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; CHECK-LABEL: t_vcgth_f16:
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; CHECK: fcmp h0, h1
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; CHECK-NEXT: csetm w0, gt
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; CHECK-NEXT: ret
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entry:
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%0 = fcmp ogt half %a, %b
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%vcmpd = sext i1 %0 to i16
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ret i16 %vcmpd
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}
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define dso_local i16 @t_vcleh_f16(half %a, half %b) {
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; CHECK-LABEL: t_vcleh_f16:
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; CHECK: fcmp h0, h1
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; CHECK-NEXT: csetm w0, ls
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; CHECK-NEXT: ret
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entry:
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%0 = fcmp ole half %a, %b
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%vcmpd = sext i1 %0 to i16
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ret i16 %vcmpd
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}
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define dso_local i16 @t_vclth_f16(half %a, half %b) {
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; CHECK-LABEL: t_vclth_f16:
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; CHECK: fcmp h0, h1
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; CHECK-NEXT: csetm w0, mi
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; CHECK-NEXT: ret
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entry:
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%0 = fcmp olt half %a, %b
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%vcmpd = sext i1 %0 to i16
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ret i16 %vcmpd
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}
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define dso_local half @t_vmaxh_f16(half %a, half %b) {
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; CHECK-LABEL: t_vmaxh_f16:
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; CHECK: fmax h0, h0, h1
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; CHECK-NEXT: ret
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entry:
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%vmax = tail call half @llvm.aarch64.neon.fmax.f16(half %a, half %b)
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ret half %vmax
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}
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define dso_local half @t_vminh_f16(half %a, half %b) {
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; CHECK-LABEL: t_vminh_f16:
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; CHECK: fmin h0, h0, h1
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; CHECK-NEXT: ret
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entry:
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%vmin = tail call half @llvm.aarch64.neon.fmin.f16(half %a, half %b)
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ret half %vmin
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}
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define dso_local half @t_vmulxh_f16(half %a, half %b) {
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; CHECK-LABEL: t_vmulxh_f16:
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; CHECK: fmulx h0, h0, h1
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; CHECK-NEXT: ret
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entry:
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%vmulxh_f16 = tail call half @llvm.aarch64.neon.fmulx.f16(half %a, half %b)
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ret half %vmulxh_f16
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}
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define dso_local half @t_vrecpsh_f16(half %a, half %b) {
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; CHECK-LABEL: t_vrecpsh_f16:
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; CHECK: frecps h0, h0, h1
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; CHECK-NEXT: ret
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entry:
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%vrecps = tail call half @llvm.aarch64.neon.frecps.f16(half %a, half %b)
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ret half %vrecps
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}
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define dso_local half @t_vrsqrtsh_f16(half %a, half %b) {
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; CHECK-LABEL: t_vrsqrtsh_f16:
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; CHECK: frsqrts h0, h0, h1
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; CHECK-NEXT: ret
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entry:
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%vrsqrtsh_f16 = tail call half @llvm.aarch64.neon.frsqrts.f16(half %a, half %b)
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ret half %vrsqrtsh_f16
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}
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declare half @llvm.aarch64.neon.vcvtfxs2fp.f16.i32(i32, i32) #1
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declare half @llvm.aarch64.neon.vcvtfxs2fp.f16.i64(i64, i32) #1
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declare i32 @llvm.aarch64.neon.vcvtfp2fxs.i32.f16(half, i32) #1
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declare i64 @llvm.aarch64.neon.vcvtfp2fxs.i64.f16(half, i32) #1
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declare half @llvm.aarch64.neon.vcvtfxu2fp.f16.i32(i32, i32) #1
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declare i32 @llvm.aarch64.neon.vcvtfp2fxu.i32.f16(half, i32) #1
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define dso_local half @test_vcvth_n_f16_s16_1(i16 %a) {
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; CHECK-LABEL: test_vcvth_n_f16_s16_1:
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; CHECK: fmov s0, w[[wReg:[0-9]+]]
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; CHECK-NEXT: scvtf h0, h0, #1
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; CHECK-NEXT: ret
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entry:
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%sext = sext i16 %a to i32
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%fcvth_n = tail call half @llvm.aarch64.neon.vcvtfxs2fp.f16.i32(i32 %sext, i32 1)
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ret half %fcvth_n
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}
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define dso_local half @test_vcvth_n_f16_s16_16(i16 %a) {
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; CHECK-LABEL: test_vcvth_n_f16_s16_16:
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; CHECK: fmov s0, w[[wReg:[0-9]+]]
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; CHECK-NEXT: scvtf h0, h0, #16
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; CHECK-NEXT: ret
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entry:
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%sext = sext i16 %a to i32
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%fcvth_n = tail call half @llvm.aarch64.neon.vcvtfxs2fp.f16.i32(i32 %sext, i32 16)
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ret half %fcvth_n
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}
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define dso_local half @test_vcvth_n_f16_s32_1(i32 %a) {
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; CHECK-LABEL: test_vcvth_n_f16_s32_1:
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; CHECK: fmov s0, w0
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; CHECK-NEXT: scvtf h0, h0, #1
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; CHECK-NEXT: ret
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entry:
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%vcvth_n_f16_s32 = tail call half @llvm.aarch64.neon.vcvtfxs2fp.f16.i32(i32 %a, i32 1)
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ret half %vcvth_n_f16_s32
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}
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define dso_local half @test_vcvth_n_f16_s32_16(i32 %a) {
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; CHECK-LABEL: test_vcvth_n_f16_s32_16:
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; CHECK: fmov s0, w0
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; CHECK-NEXT: scvtf h0, h0, #16
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; CHECK-NEXT: ret
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entry:
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%vcvth_n_f16_s32 = tail call half @llvm.aarch64.neon.vcvtfxs2fp.f16.i32(i32 %a, i32 16)
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ret half %vcvth_n_f16_s32
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}
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define dso_local i16 @test_vcvth_n_s16_f16_1(half %a) {
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; CHECK-LABEL: test_vcvth_n_s16_f16_1:
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; CHECK: fcvtzs h0, h0, #1
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; CHECK-NEXT: fmov w0, s0
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; CHECK-NEXT: ret
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entry:
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%fcvth_n = tail call i32 @llvm.aarch64.neon.vcvtfp2fxs.i32.f16(half %a, i32 1)
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%0 = trunc i32 %fcvth_n to i16
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ret i16 %0
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}
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define dso_local i16 @test_vcvth_n_s16_f16_16(half %a) {
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; CHECK-LABEL: test_vcvth_n_s16_f16_16:
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; CHECK: fcvtzs h0, h0, #16
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; CHECK-NEXT: fmov w0, s0
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; CHECK-NEXT: ret
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entry:
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%fcvth_n = tail call i32 @llvm.aarch64.neon.vcvtfp2fxs.i32.f16(half %a, i32 16)
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%0 = trunc i32 %fcvth_n to i16
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ret i16 %0
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}
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define dso_local i32 @test_vcvth_n_s32_f16_1(half %a) {
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; CHECK-LABEL: test_vcvth_n_s32_f16_1:
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; CHECK: fcvtzs h0, h0, #1
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; CHECK-NEXT: fmov w0, s0
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; CHECK-NEXT: ret
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entry:
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%vcvth_n_s32_f16 = tail call i32 @llvm.aarch64.neon.vcvtfp2fxs.i32.f16(half %a, i32 1)
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ret i32 %vcvth_n_s32_f16
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}
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define dso_local i32 @test_vcvth_n_s32_f16_16(half %a) {
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; CHECK-LABEL: test_vcvth_n_s32_f16_16:
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; CHECK: fcvtzs h0, h0, #16
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; CHECK-NEXT: fmov w0, s0
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; CHECK-NEXT: ret
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entry:
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%vcvth_n_s32_f16 = tail call i32 @llvm.aarch64.neon.vcvtfp2fxs.i32.f16(half %a, i32 16)
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ret i32 %vcvth_n_s32_f16
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}
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define dso_local i64 @test_vcvth_n_s64_f16_1(half %a) {
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; CHECK-LABEL: test_vcvth_n_s64_f16_1:
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; CHECK: fcvtzs h0, h0, #1
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; CHECK-NEXT: fmov x0, d0
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; CHECK-NEXT: ret
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entry:
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%vcvth_n_s64_f16 = tail call i64 @llvm.aarch64.neon.vcvtfp2fxs.i64.f16(half %a, i32 1)
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ret i64 %vcvth_n_s64_f16
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}
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define dso_local i64 @test_vcvth_n_s64_f16_32(half %a) {
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; CHECK-LABEL: test_vcvth_n_s64_f16_32:
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; CHECK: fcvtzs h0, h0, #32
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; CHECK-NEXT: fmov x0, d0
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; CHECK-NEXT: ret
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entry:
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%vcvth_n_s64_f16 = tail call i64 @llvm.aarch64.neon.vcvtfp2fxs.i64.f16(half %a, i32 32)
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ret i64 %vcvth_n_s64_f16
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}
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define dso_local half @test_vcvth_n_f16_u16_1(i16 %a) {
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; CHECK-LABEL: test_vcvth_n_f16_u16_1:
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; CHECK: ucvtf h0, h0, #1
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; CHECK-NEXT: ret
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entry:
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%0 = zext i16 %a to i32
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%fcvth_n = tail call half @llvm.aarch64.neon.vcvtfxu2fp.f16.i32(i32 %0, i32 1)
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ret half %fcvth_n
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}
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define dso_local half @test_vcvth_n_f16_u16_16(i16 %a) {
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; CHECK-LABEL: test_vcvth_n_f16_u16_16:
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; CHECK: ucvtf h0, h0, #16
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; CHECK-NEXT: ret
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entry:
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%0 = zext i16 %a to i32
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%fcvth_n = tail call half @llvm.aarch64.neon.vcvtfxu2fp.f16.i32(i32 %0, i32 16)
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ret half %fcvth_n
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}
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define dso_local half @test_vcvth_n_f16_u32_1(i32 %a) {
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; CHECK-LABEL: test_vcvth_n_f16_u32_1:
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; CHECK: fmov s0, w0
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; CHECK-NEXT: ucvtf h0, h0, #1
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; CHECK-NEXT: ret
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entry:
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%vcvth_n_f16_u32 = tail call half @llvm.aarch64.neon.vcvtfxu2fp.f16.i32(i32 %a, i32 1)
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ret half %vcvth_n_f16_u32
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}
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define dso_local half @test_vcvth_n_f16_u32_16(i32 %a) {
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; CHECK-LABEL: test_vcvth_n_f16_u32_16:
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; CHECK: ucvtf h0, h0, #16
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; CHECK-NEXT: ret
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entry:
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%vcvth_n_f16_u32 = tail call half @llvm.aarch64.neon.vcvtfxu2fp.f16.i32(i32 %a, i32 16)
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ret half %vcvth_n_f16_u32
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}
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define dso_local i16 @test_vcvth_n_u16_f16_1(half %a) {
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; CHECK-LABEL: test_vcvth_n_u16_f16_1:
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; CHECK: fcvtzu h0, h0, #1
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; CHECK-NEXT: fmov w0, s0
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; CHECK-NEXT: ret
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entry:
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%fcvth_n = tail call i32 @llvm.aarch64.neon.vcvtfp2fxu.i32.f16(half %a, i32 1)
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%0 = trunc i32 %fcvth_n to i16
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ret i16 %0
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}
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define dso_local i16 @test_vcvth_n_u16_f16_16(half %a) {
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; CHECK-LABEL: test_vcvth_n_u16_f16_16:
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; CHECK: fcvtzu h0, h0, #16
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; CHECK-NEXT: fmov w0, s0
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; CHECK-NEXT: ret
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entry:
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%fcvth_n = tail call i32 @llvm.aarch64.neon.vcvtfp2fxu.i32.f16(half %a, i32 16)
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%0 = trunc i32 %fcvth_n to i16
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ret i16 %0
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}
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define dso_local i32 @test_vcvth_n_u32_f16_1(half %a) {
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; CHECK-LABEL: test_vcvth_n_u32_f16_1:
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; CHECK: fcvtzu h0, h0, #1
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; CHECK-NEXT: fmov w0, s0
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; CHECK-NEXT: ret
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entry:
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%vcvth_n_u32_f16 = tail call i32 @llvm.aarch64.neon.vcvtfp2fxu.i32.f16(half %a, i32 1)
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ret i32 %vcvth_n_u32_f16
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}
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define dso_local i32 @test_vcvth_n_u32_f16_16(half %a) {
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; CHECK-LABEL: test_vcvth_n_u32_f16_16:
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; CHECK: fcvtzu h0, h0, #16
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; CHECK-NEXT: fmov w0, s0
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; CHECK-NEXT: ret
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entry:
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%vcvth_n_u32_f16 = tail call i32 @llvm.aarch64.neon.vcvtfp2fxu.i32.f16(half %a, i32 16)
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ret i32 %vcvth_n_u32_f16
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}
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define dso_local i16 @vcageh_f16_test(half %a, half %b) {
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; CHECK-LABEL: vcageh_f16_test:
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; CHECK: facge h0, h0, h1
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; CHECK-NEXT: fmov w0, s0
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; CHECK-NEXT: ret
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entry:
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%facg = tail call i32 @llvm.aarch64.neon.facge.i32.f16(half %a, half %b)
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%0 = trunc i32 %facg to i16
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ret i16 %0
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}
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define dso_local i16 @vcagth_f16_test(half %a, half %b) {
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; CHECK-LABEL: vcagth_f16_test:
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; CHECK: facgt h0, h0, h1
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; CHECK-NEXT: fmov w0, s0
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; CHECK-NEXT: ret
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entry:
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%facg = tail call i32 @llvm.aarch64.neon.facgt.i32.f16(half %a, half %b)
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%0 = trunc i32 %facg to i16
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ret i16 %0
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}
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define dso_local half @vcvth_n_f16_s64_test(i64 %a) {
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; CHECK-LABEL: vcvth_n_f16_s64_test:
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; CHECK: fmov d0, x0
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; CHECK-NEXT: scvtf h0, h0, #16
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; CHECK-NEXT: ret
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entry:
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%vcvth_n_f16_s64 = tail call half @llvm.aarch64.neon.vcvtfxs2fp.f16.i64(i64 %a, i32 16)
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ret half %vcvth_n_f16_s64
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}
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