forked from OSchip/llvm-project
615 lines
25 KiB
C++
615 lines
25 KiB
C++
//=- AArch64/AArch64MCCodeEmitter.cpp - Convert AArch64 code to machine code-=//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the AArch64MCCodeEmitter class.
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//
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//===----------------------------------------------------------------------===//
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#include "MCTargetDesc/AArch64AddressingModes.h"
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#include "MCTargetDesc/AArch64FixupKinds.h"
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#include "MCTargetDesc/AArch64MCExpr.h"
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#include "Utils/AArch64BaseInfo.h"
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/ADT/Statistic.h"
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#include "llvm/MC/MCCodeEmitter.h"
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#include "llvm/MC/MCContext.h"
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#include "llvm/MC/MCFixup.h"
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#include "llvm/MC/MCInst.h"
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#include "llvm/MC/MCInstrInfo.h"
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#include "llvm/MC/MCRegisterInfo.h"
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#include "llvm/MC/MCSubtargetInfo.h"
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#include "llvm/Support/Casting.h"
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#include "llvm/Support/Endian.h"
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#include "llvm/Support/EndianStream.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/raw_ostream.h"
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#include <cassert>
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#include <cstdint>
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using namespace llvm;
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#define DEBUG_TYPE "mccodeemitter"
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STATISTIC(MCNumEmitted, "Number of MC instructions emitted.");
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STATISTIC(MCNumFixups, "Number of MC fixups created.");
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namespace {
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class AArch64MCCodeEmitter : public MCCodeEmitter {
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MCContext &Ctx;
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const MCInstrInfo &MCII;
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public:
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AArch64MCCodeEmitter(const MCInstrInfo &mcii, MCContext &ctx)
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: Ctx(ctx), MCII(mcii) {}
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AArch64MCCodeEmitter(const AArch64MCCodeEmitter &) = delete;
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void operator=(const AArch64MCCodeEmitter &) = delete;
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~AArch64MCCodeEmitter() override = default;
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// getBinaryCodeForInstr - TableGen'erated function for getting the
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// binary encoding for an instruction.
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uint64_t getBinaryCodeForInstr(const MCInst &MI,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const;
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/// getMachineOpValue - Return binary encoding of operand. If the machine
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/// operand requires relocation, record the relocation and return zero.
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unsigned getMachineOpValue(const MCInst &MI, const MCOperand &MO,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const;
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/// getLdStUImm12OpValue - Return encoding info for 12-bit unsigned immediate
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/// attached to a load, store or prfm instruction. If operand requires a
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/// relocation, record it and return zero in that part of the encoding.
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template <uint32_t FixupKind>
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uint32_t getLdStUImm12OpValue(const MCInst &MI, unsigned OpIdx,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const;
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/// getAdrLabelOpValue - Return encoding info for 21-bit immediate ADR label
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/// target.
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uint32_t getAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const;
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/// getAddSubImmOpValue - Return encoding for the 12-bit immediate value and
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/// the 2-bit shift field.
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uint32_t getAddSubImmOpValue(const MCInst &MI, unsigned OpIdx,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const;
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/// getCondBranchTargetOpValue - Return the encoded value for a conditional
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/// branch target.
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uint32_t getCondBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const;
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/// getLoadLiteralOpValue - Return the encoded value for a load-literal
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/// pc-relative address.
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uint32_t getLoadLiteralOpValue(const MCInst &MI, unsigned OpIdx,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const;
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/// getMemExtendOpValue - Return the encoded value for a reg-extend load/store
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/// instruction: bit 0 is whether a shift is present, bit 1 is whether the
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/// operation is a sign extend (as opposed to a zero extend).
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uint32_t getMemExtendOpValue(const MCInst &MI, unsigned OpIdx,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const;
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/// getTestBranchTargetOpValue - Return the encoded value for a test-bit-and-
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/// branch target.
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uint32_t getTestBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const;
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/// getBranchTargetOpValue - Return the encoded value for an unconditional
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/// branch target.
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uint32_t getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const;
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/// getMoveWideImmOpValue - Return the encoded value for the immediate operand
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/// of a MOVZ or MOVK instruction.
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uint32_t getMoveWideImmOpValue(const MCInst &MI, unsigned OpIdx,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const;
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/// getVecShifterOpValue - Return the encoded value for the vector shifter.
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uint32_t getVecShifterOpValue(const MCInst &MI, unsigned OpIdx,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const;
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/// getMoveVecShifterOpValue - Return the encoded value for the vector move
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/// shifter (MSL).
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uint32_t getMoveVecShifterOpValue(const MCInst &MI, unsigned OpIdx,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const;
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/// getFixedPointScaleOpValue - Return the encoded value for the
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// FP-to-fixed-point scale factor.
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uint32_t getFixedPointScaleOpValue(const MCInst &MI, unsigned OpIdx,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const;
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uint32_t getVecShiftR64OpValue(const MCInst &MI, unsigned OpIdx,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const;
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uint32_t getVecShiftR32OpValue(const MCInst &MI, unsigned OpIdx,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const;
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uint32_t getVecShiftR16OpValue(const MCInst &MI, unsigned OpIdx,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const;
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uint32_t getVecShiftR8OpValue(const MCInst &MI, unsigned OpIdx,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const;
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uint32_t getVecShiftL64OpValue(const MCInst &MI, unsigned OpIdx,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const;
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uint32_t getVecShiftL32OpValue(const MCInst &MI, unsigned OpIdx,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const;
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uint32_t getVecShiftL16OpValue(const MCInst &MI, unsigned OpIdx,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const;
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uint32_t getVecShiftL8OpValue(const MCInst &MI, unsigned OpIdx,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const;
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unsigned fixMOVZ(const MCInst &MI, unsigned EncodedValue,
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const MCSubtargetInfo &STI) const;
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void encodeInstruction(const MCInst &MI, raw_ostream &OS,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const override;
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unsigned fixMulHigh(const MCInst &MI, unsigned EncodedValue,
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const MCSubtargetInfo &STI) const;
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template<int hasRs, int hasRt2> unsigned
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fixLoadStoreExclusive(const MCInst &MI, unsigned EncodedValue,
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const MCSubtargetInfo &STI) const;
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unsigned fixOneOperandFPComparison(const MCInst &MI, unsigned EncodedValue,
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const MCSubtargetInfo &STI) const;
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private:
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uint64_t computeAvailableFeatures(const FeatureBitset &FB) const;
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void verifyInstructionPredicates(const MCInst &MI,
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uint64_t AvailableFeatures) const;
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};
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} // end anonymous namespace
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/// getMachineOpValue - Return binary encoding of operand. If the machine
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/// operand requires relocation, record the relocation and return zero.
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unsigned
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AArch64MCCodeEmitter::getMachineOpValue(const MCInst &MI, const MCOperand &MO,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const {
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if (MO.isReg())
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return Ctx.getRegisterInfo()->getEncodingValue(MO.getReg());
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assert(MO.isImm() && "did not expect relocated expression");
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return static_cast<unsigned>(MO.getImm());
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}
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template<unsigned FixupKind> uint32_t
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AArch64MCCodeEmitter::getLdStUImm12OpValue(const MCInst &MI, unsigned OpIdx,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const {
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const MCOperand &MO = MI.getOperand(OpIdx);
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uint32_t ImmVal = 0;
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if (MO.isImm())
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ImmVal = static_cast<uint32_t>(MO.getImm());
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else {
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assert(MO.isExpr() && "unable to encode load/store imm operand");
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MCFixupKind Kind = MCFixupKind(FixupKind);
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Fixups.push_back(MCFixup::create(0, MO.getExpr(), Kind, MI.getLoc()));
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++MCNumFixups;
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}
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return ImmVal;
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}
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/// getAdrLabelOpValue - Return encoding info for 21-bit immediate ADR label
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/// target.
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uint32_t
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AArch64MCCodeEmitter::getAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const {
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const MCOperand &MO = MI.getOperand(OpIdx);
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// If the destination is an immediate, we have nothing to do.
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if (MO.isImm())
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return MO.getImm();
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assert(MO.isExpr() && "Unexpected target type!");
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const MCExpr *Expr = MO.getExpr();
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MCFixupKind Kind = MI.getOpcode() == AArch64::ADR
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? MCFixupKind(AArch64::fixup_aarch64_pcrel_adr_imm21)
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: MCFixupKind(AArch64::fixup_aarch64_pcrel_adrp_imm21);
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Fixups.push_back(MCFixup::create(0, Expr, Kind, MI.getLoc()));
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MCNumFixups += 1;
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// All of the information is in the fixup.
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return 0;
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}
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/// getAddSubImmOpValue - Return encoding for the 12-bit immediate value and
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/// the 2-bit shift field. The shift field is stored in bits 13-14 of the
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/// return value.
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uint32_t
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AArch64MCCodeEmitter::getAddSubImmOpValue(const MCInst &MI, unsigned OpIdx,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const {
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// Suboperands are [imm, shifter].
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const MCOperand &MO = MI.getOperand(OpIdx);
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const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
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assert(AArch64_AM::getShiftType(MO1.getImm()) == AArch64_AM::LSL &&
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"unexpected shift type for add/sub immediate");
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unsigned ShiftVal = AArch64_AM::getShiftValue(MO1.getImm());
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assert((ShiftVal == 0 || ShiftVal == 12) &&
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"unexpected shift value for add/sub immediate");
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if (MO.isImm())
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return MO.getImm() | (ShiftVal == 0 ? 0 : (1 << ShiftVal));
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assert(MO.isExpr() && "Unable to encode MCOperand!");
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const MCExpr *Expr = MO.getExpr();
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// Encode the 12 bits of the fixup.
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MCFixupKind Kind = MCFixupKind(AArch64::fixup_aarch64_add_imm12);
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Fixups.push_back(MCFixup::create(0, Expr, Kind, MI.getLoc()));
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++MCNumFixups;
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// Set the shift bit of the add instruction for relocation types
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// R_AARCH64_TLSLE_ADD_TPREL_HI12 and R_AARCH64_TLSLD_ADD_DTPREL_HI12.
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if (const AArch64MCExpr *A64E = dyn_cast<AArch64MCExpr>(Expr)) {
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AArch64MCExpr::VariantKind RefKind = A64E->getKind();
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if (RefKind == AArch64MCExpr::VK_TPREL_HI12 ||
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RefKind == AArch64MCExpr::VK_DTPREL_HI12 ||
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RefKind == AArch64MCExpr::VK_SECREL_HI12)
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ShiftVal = 12;
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}
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return ShiftVal == 0 ? 0 : (1 << ShiftVal);
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}
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/// getCondBranchTargetOpValue - Return the encoded value for a conditional
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/// branch target.
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uint32_t AArch64MCCodeEmitter::getCondBranchTargetOpValue(
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const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const {
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const MCOperand &MO = MI.getOperand(OpIdx);
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// If the destination is an immediate, we have nothing to do.
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if (MO.isImm())
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return MO.getImm();
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assert(MO.isExpr() && "Unexpected target type!");
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MCFixupKind Kind = MCFixupKind(AArch64::fixup_aarch64_pcrel_branch19);
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Fixups.push_back(MCFixup::create(0, MO.getExpr(), Kind, MI.getLoc()));
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++MCNumFixups;
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// All of the information is in the fixup.
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return 0;
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}
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/// getLoadLiteralOpValue - Return the encoded value for a load-literal
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/// pc-relative address.
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uint32_t
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AArch64MCCodeEmitter::getLoadLiteralOpValue(const MCInst &MI, unsigned OpIdx,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const {
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const MCOperand &MO = MI.getOperand(OpIdx);
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// If the destination is an immediate, we have nothing to do.
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if (MO.isImm())
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return MO.getImm();
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assert(MO.isExpr() && "Unexpected target type!");
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MCFixupKind Kind = MCFixupKind(AArch64::fixup_aarch64_ldr_pcrel_imm19);
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Fixups.push_back(MCFixup::create(0, MO.getExpr(), Kind, MI.getLoc()));
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++MCNumFixups;
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// All of the information is in the fixup.
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return 0;
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}
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uint32_t
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AArch64MCCodeEmitter::getMemExtendOpValue(const MCInst &MI, unsigned OpIdx,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const {
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unsigned SignExtend = MI.getOperand(OpIdx).getImm();
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unsigned DoShift = MI.getOperand(OpIdx + 1).getImm();
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return (SignExtend << 1) | DoShift;
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}
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uint32_t
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AArch64MCCodeEmitter::getMoveWideImmOpValue(const MCInst &MI, unsigned OpIdx,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const {
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const MCOperand &MO = MI.getOperand(OpIdx);
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if (MO.isImm())
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return MO.getImm();
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assert(MO.isExpr() && "Unexpected movz/movk immediate");
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Fixups.push_back(MCFixup::create(
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0, MO.getExpr(), MCFixupKind(AArch64::fixup_aarch64_movw), MI.getLoc()));
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++MCNumFixups;
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return 0;
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}
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/// getTestBranchTargetOpValue - Return the encoded value for a test-bit-and-
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/// branch target.
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uint32_t AArch64MCCodeEmitter::getTestBranchTargetOpValue(
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const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const {
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const MCOperand &MO = MI.getOperand(OpIdx);
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// If the destination is an immediate, we have nothing to do.
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if (MO.isImm())
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return MO.getImm();
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assert(MO.isExpr() && "Unexpected ADR target type!");
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MCFixupKind Kind = MCFixupKind(AArch64::fixup_aarch64_pcrel_branch14);
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Fixups.push_back(MCFixup::create(0, MO.getExpr(), Kind, MI.getLoc()));
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++MCNumFixups;
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// All of the information is in the fixup.
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return 0;
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}
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/// getBranchTargetOpValue - Return the encoded value for an unconditional
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/// branch target.
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uint32_t
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AArch64MCCodeEmitter::getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const {
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const MCOperand &MO = MI.getOperand(OpIdx);
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// If the destination is an immediate, we have nothing to do.
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if (MO.isImm())
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return MO.getImm();
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assert(MO.isExpr() && "Unexpected ADR target type!");
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MCFixupKind Kind = MI.getOpcode() == AArch64::BL
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? MCFixupKind(AArch64::fixup_aarch64_pcrel_call26)
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: MCFixupKind(AArch64::fixup_aarch64_pcrel_branch26);
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Fixups.push_back(MCFixup::create(0, MO.getExpr(), Kind, MI.getLoc()));
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++MCNumFixups;
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// All of the information is in the fixup.
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return 0;
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}
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/// getVecShifterOpValue - Return the encoded value for the vector shifter:
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///
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/// 00 -> 0
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/// 01 -> 8
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/// 10 -> 16
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/// 11 -> 24
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uint32_t
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AArch64MCCodeEmitter::getVecShifterOpValue(const MCInst &MI, unsigned OpIdx,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const {
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const MCOperand &MO = MI.getOperand(OpIdx);
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assert(MO.isImm() && "Expected an immediate value for the shift amount!");
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switch (MO.getImm()) {
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default:
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break;
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case 0:
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return 0;
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case 8:
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return 1;
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case 16:
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return 2;
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case 24:
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return 3;
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}
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llvm_unreachable("Invalid value for vector shift amount!");
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}
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/// getFixedPointScaleOpValue - Return the encoded value for the
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// FP-to-fixed-point scale factor.
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uint32_t AArch64MCCodeEmitter::getFixedPointScaleOpValue(
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const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const {
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const MCOperand &MO = MI.getOperand(OpIdx);
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assert(MO.isImm() && "Expected an immediate value for the scale amount!");
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return 64 - MO.getImm();
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}
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uint32_t
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AArch64MCCodeEmitter::getVecShiftR64OpValue(const MCInst &MI, unsigned OpIdx,
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SmallVectorImpl<MCFixup> &Fixups,
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|
const MCSubtargetInfo &STI) const {
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|
const MCOperand &MO = MI.getOperand(OpIdx);
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assert(MO.isImm() && "Expected an immediate value for the scale amount!");
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return 64 - MO.getImm();
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}
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|
|
|
uint32_t
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AArch64MCCodeEmitter::getVecShiftR32OpValue(const MCInst &MI, unsigned OpIdx,
|
|
SmallVectorImpl<MCFixup> &Fixups,
|
|
const MCSubtargetInfo &STI) const {
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|
const MCOperand &MO = MI.getOperand(OpIdx);
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assert(MO.isImm() && "Expected an immediate value for the scale amount!");
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|
return 32 - MO.getImm();
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}
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|
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|
uint32_t
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|
AArch64MCCodeEmitter::getVecShiftR16OpValue(const MCInst &MI, unsigned OpIdx,
|
|
SmallVectorImpl<MCFixup> &Fixups,
|
|
const MCSubtargetInfo &STI) const {
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|
const MCOperand &MO = MI.getOperand(OpIdx);
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assert(MO.isImm() && "Expected an immediate value for the scale amount!");
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|
return 16 - MO.getImm();
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|
}
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|
|
|
uint32_t
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|
AArch64MCCodeEmitter::getVecShiftR8OpValue(const MCInst &MI, unsigned OpIdx,
|
|
SmallVectorImpl<MCFixup> &Fixups,
|
|
const MCSubtargetInfo &STI) const {
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|
const MCOperand &MO = MI.getOperand(OpIdx);
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|
assert(MO.isImm() && "Expected an immediate value for the scale amount!");
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|
return 8 - MO.getImm();
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|
}
|
|
|
|
uint32_t
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|
AArch64MCCodeEmitter::getVecShiftL64OpValue(const MCInst &MI, unsigned OpIdx,
|
|
SmallVectorImpl<MCFixup> &Fixups,
|
|
const MCSubtargetInfo &STI) const {
|
|
const MCOperand &MO = MI.getOperand(OpIdx);
|
|
assert(MO.isImm() && "Expected an immediate value for the scale amount!");
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|
return MO.getImm() - 64;
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|
}
|
|
|
|
uint32_t
|
|
AArch64MCCodeEmitter::getVecShiftL32OpValue(const MCInst &MI, unsigned OpIdx,
|
|
SmallVectorImpl<MCFixup> &Fixups,
|
|
const MCSubtargetInfo &STI) const {
|
|
const MCOperand &MO = MI.getOperand(OpIdx);
|
|
assert(MO.isImm() && "Expected an immediate value for the scale amount!");
|
|
return MO.getImm() - 32;
|
|
}
|
|
|
|
uint32_t
|
|
AArch64MCCodeEmitter::getVecShiftL16OpValue(const MCInst &MI, unsigned OpIdx,
|
|
SmallVectorImpl<MCFixup> &Fixups,
|
|
const MCSubtargetInfo &STI) const {
|
|
const MCOperand &MO = MI.getOperand(OpIdx);
|
|
assert(MO.isImm() && "Expected an immediate value for the scale amount!");
|
|
return MO.getImm() - 16;
|
|
}
|
|
|
|
uint32_t
|
|
AArch64MCCodeEmitter::getVecShiftL8OpValue(const MCInst &MI, unsigned OpIdx,
|
|
SmallVectorImpl<MCFixup> &Fixups,
|
|
const MCSubtargetInfo &STI) const {
|
|
const MCOperand &MO = MI.getOperand(OpIdx);
|
|
assert(MO.isImm() && "Expected an immediate value for the scale amount!");
|
|
return MO.getImm() - 8;
|
|
}
|
|
|
|
/// getMoveVecShifterOpValue - Return the encoded value for the vector move
|
|
/// shifter (MSL).
|
|
uint32_t AArch64MCCodeEmitter::getMoveVecShifterOpValue(
|
|
const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups,
|
|
const MCSubtargetInfo &STI) const {
|
|
const MCOperand &MO = MI.getOperand(OpIdx);
|
|
assert(MO.isImm() &&
|
|
"Expected an immediate value for the move shift amount!");
|
|
unsigned ShiftVal = AArch64_AM::getShiftValue(MO.getImm());
|
|
assert((ShiftVal == 8 || ShiftVal == 16) && "Invalid shift amount!");
|
|
return ShiftVal == 8 ? 0 : 1;
|
|
}
|
|
|
|
unsigned AArch64MCCodeEmitter::fixMOVZ(const MCInst &MI, unsigned EncodedValue,
|
|
const MCSubtargetInfo &STI) const {
|
|
// If one of the signed fixup kinds is applied to a MOVZ instruction, the
|
|
// eventual result could be either a MOVZ or a MOVN. It's the MCCodeEmitter's
|
|
// job to ensure that any bits possibly affected by this are 0. This means we
|
|
// must zero out bit 30 (essentially emitting a MOVN).
|
|
MCOperand UImm16MO = MI.getOperand(1);
|
|
|
|
// Nothing to do if there's no fixup.
|
|
if (UImm16MO.isImm())
|
|
return EncodedValue;
|
|
|
|
const AArch64MCExpr *A64E = cast<AArch64MCExpr>(UImm16MO.getExpr());
|
|
switch (A64E->getKind()) {
|
|
case AArch64MCExpr::VK_DTPREL_G2:
|
|
case AArch64MCExpr::VK_DTPREL_G1:
|
|
case AArch64MCExpr::VK_DTPREL_G0:
|
|
case AArch64MCExpr::VK_GOTTPREL_G1:
|
|
case AArch64MCExpr::VK_TPREL_G2:
|
|
case AArch64MCExpr::VK_TPREL_G1:
|
|
case AArch64MCExpr::VK_TPREL_G0:
|
|
return EncodedValue & ~(1u << 30);
|
|
default:
|
|
// Nothing to do for an unsigned fixup.
|
|
return EncodedValue;
|
|
}
|
|
|
|
|
|
return EncodedValue & ~(1u << 30);
|
|
}
|
|
|
|
void AArch64MCCodeEmitter::encodeInstruction(const MCInst &MI, raw_ostream &OS,
|
|
SmallVectorImpl<MCFixup> &Fixups,
|
|
const MCSubtargetInfo &STI) const {
|
|
verifyInstructionPredicates(MI,
|
|
computeAvailableFeatures(STI.getFeatureBits()));
|
|
|
|
if (MI.getOpcode() == AArch64::TLSDESCCALL) {
|
|
// This is a directive which applies an R_AARCH64_TLSDESC_CALL to the
|
|
// following (BLR) instruction. It doesn't emit any code itself so it
|
|
// doesn't go through the normal TableGenerated channels.
|
|
MCFixupKind Fixup = MCFixupKind(AArch64::fixup_aarch64_tlsdesc_call);
|
|
Fixups.push_back(MCFixup::create(0, MI.getOperand(0).getExpr(), Fixup));
|
|
return;
|
|
} else if (MI.getOpcode() == AArch64::CompilerBarrier) {
|
|
// This just prevents the compiler from reordering accesses, no actual code.
|
|
return;
|
|
}
|
|
|
|
uint64_t Binary = getBinaryCodeForInstr(MI, Fixups, STI);
|
|
support::endian::Writer<support::little>(OS).write<uint32_t>(Binary);
|
|
++MCNumEmitted; // Keep track of the # of mi's emitted.
|
|
}
|
|
|
|
unsigned
|
|
AArch64MCCodeEmitter::fixMulHigh(const MCInst &MI,
|
|
unsigned EncodedValue,
|
|
const MCSubtargetInfo &STI) const {
|
|
// The Ra field of SMULH and UMULH is unused: it should be assembled as 31
|
|
// (i.e. all bits 1) but is ignored by the processor.
|
|
EncodedValue |= 0x1f << 10;
|
|
return EncodedValue;
|
|
}
|
|
|
|
template<int hasRs, int hasRt2> unsigned
|
|
AArch64MCCodeEmitter::fixLoadStoreExclusive(const MCInst &MI,
|
|
unsigned EncodedValue,
|
|
const MCSubtargetInfo &STI) const {
|
|
if (!hasRs) EncodedValue |= 0x001F0000;
|
|
if (!hasRt2) EncodedValue |= 0x00007C00;
|
|
|
|
return EncodedValue;
|
|
}
|
|
|
|
unsigned AArch64MCCodeEmitter::fixOneOperandFPComparison(
|
|
const MCInst &MI, unsigned EncodedValue, const MCSubtargetInfo &STI) const {
|
|
// The Rm field of FCMP and friends is unused - it should be assembled
|
|
// as 0, but is ignored by the processor.
|
|
EncodedValue &= ~(0x1f << 16);
|
|
return EncodedValue;
|
|
}
|
|
|
|
#define ENABLE_INSTR_PREDICATE_VERIFIER
|
|
#include "AArch64GenMCCodeEmitter.inc"
|
|
|
|
MCCodeEmitter *llvm::createAArch64MCCodeEmitter(const MCInstrInfo &MCII,
|
|
const MCRegisterInfo &MRI,
|
|
MCContext &Ctx) {
|
|
return new AArch64MCCodeEmitter(MCII, Ctx);
|
|
}
|