forked from OSchip/llvm-project
614 lines
21 KiB
C++
614 lines
21 KiB
C++
//===-- SystemZInstrInfo.cpp - SystemZ instruction information ------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the SystemZ implementation of the TargetInstrInfo class.
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//
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//===----------------------------------------------------------------------===//
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#include "SystemZInstrInfo.h"
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#include "SystemZInstrBuilder.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/Target/TargetMachine.h"
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#define GET_INSTRINFO_CTOR
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#define GET_INSTRMAP_INFO
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#include "SystemZGenInstrInfo.inc"
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using namespace llvm;
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SystemZInstrInfo::SystemZInstrInfo(SystemZTargetMachine &tm)
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: SystemZGenInstrInfo(SystemZ::ADJCALLSTACKDOWN, SystemZ::ADJCALLSTACKUP),
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RI(tm) {
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}
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// MI is a 128-bit load or store. Split it into two 64-bit loads or stores,
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// each having the opcode given by NewOpcode.
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void SystemZInstrInfo::splitMove(MachineBasicBlock::iterator MI,
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unsigned NewOpcode) const {
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MachineBasicBlock *MBB = MI->getParent();
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MachineFunction &MF = *MBB->getParent();
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// Get two load or store instructions. Use the original instruction for one
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// of them (arbitarily the second here) and create a clone for the other.
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MachineInstr *EarlierMI = MF.CloneMachineInstr(MI);
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MBB->insert(MI, EarlierMI);
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// Set up the two 64-bit registers.
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MachineOperand &HighRegOp = EarlierMI->getOperand(0);
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MachineOperand &LowRegOp = MI->getOperand(0);
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HighRegOp.setReg(RI.getSubReg(HighRegOp.getReg(), SystemZ::subreg_high));
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LowRegOp.setReg(RI.getSubReg(LowRegOp.getReg(), SystemZ::subreg_low));
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// The address in the first (high) instruction is already correct.
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// Adjust the offset in the second (low) instruction.
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MachineOperand &HighOffsetOp = EarlierMI->getOperand(2);
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MachineOperand &LowOffsetOp = MI->getOperand(2);
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LowOffsetOp.setImm(LowOffsetOp.getImm() + 8);
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// Set the opcodes.
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unsigned HighOpcode = getOpcodeForOffset(NewOpcode, HighOffsetOp.getImm());
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unsigned LowOpcode = getOpcodeForOffset(NewOpcode, LowOffsetOp.getImm());
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assert(HighOpcode && LowOpcode && "Both offsets should be in range");
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EarlierMI->setDesc(get(HighOpcode));
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MI->setDesc(get(LowOpcode));
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}
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// Split ADJDYNALLOC instruction MI.
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void SystemZInstrInfo::splitAdjDynAlloc(MachineBasicBlock::iterator MI) const {
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MachineBasicBlock *MBB = MI->getParent();
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MachineFunction &MF = *MBB->getParent();
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MachineFrameInfo *MFFrame = MF.getFrameInfo();
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MachineOperand &OffsetMO = MI->getOperand(2);
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uint64_t Offset = (MFFrame->getMaxCallFrameSize() +
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SystemZMC::CallFrameSize +
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OffsetMO.getImm());
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unsigned NewOpcode = getOpcodeForOffset(SystemZ::LA, Offset);
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assert(NewOpcode && "No support for huge argument lists yet");
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MI->setDesc(get(NewOpcode));
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OffsetMO.setImm(Offset);
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}
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// If MI is a simple load or store for a frame object, return the register
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// it loads or stores and set FrameIndex to the index of the frame object.
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// Return 0 otherwise.
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//
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// Flag is SimpleBDXLoad for loads and SimpleBDXStore for stores.
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static int isSimpleMove(const MachineInstr *MI, int &FrameIndex,
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unsigned Flag) {
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const MCInstrDesc &MCID = MI->getDesc();
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if ((MCID.TSFlags & Flag) &&
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MI->getOperand(1).isFI() &&
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MI->getOperand(2).getImm() == 0 &&
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MI->getOperand(3).getReg() == 0) {
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FrameIndex = MI->getOperand(1).getIndex();
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return MI->getOperand(0).getReg();
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}
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return 0;
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}
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unsigned SystemZInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
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int &FrameIndex) const {
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return isSimpleMove(MI, FrameIndex, SystemZII::SimpleBDXLoad);
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}
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unsigned SystemZInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
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int &FrameIndex) const {
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return isSimpleMove(MI, FrameIndex, SystemZII::SimpleBDXStore);
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}
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bool SystemZInstrInfo::isStackSlotCopy(const MachineInstr *MI,
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int &DestFrameIndex,
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int &SrcFrameIndex) const {
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// Check for MVC 0(Length,FI1),0(FI2)
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const MachineFrameInfo *MFI = MI->getParent()->getParent()->getFrameInfo();
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if (MI->getOpcode() != SystemZ::MVC ||
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!MI->getOperand(0).isFI() ||
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MI->getOperand(1).getImm() != 0 ||
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!MI->getOperand(3).isFI() ||
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MI->getOperand(4).getImm() != 0)
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return false;
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// Check that Length covers the full slots.
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int64_t Length = MI->getOperand(2).getImm();
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unsigned FI1 = MI->getOperand(0).getIndex();
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unsigned FI2 = MI->getOperand(3).getIndex();
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if (MFI->getObjectSize(FI1) != Length ||
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MFI->getObjectSize(FI2) != Length)
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return false;
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DestFrameIndex = FI1;
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SrcFrameIndex = FI2;
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return true;
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}
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bool SystemZInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
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MachineBasicBlock *&TBB,
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MachineBasicBlock *&FBB,
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SmallVectorImpl<MachineOperand> &Cond,
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bool AllowModify) const {
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// Most of the code and comments here are boilerplate.
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// Start from the bottom of the block and work up, examining the
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// terminator instructions.
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MachineBasicBlock::iterator I = MBB.end();
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while (I != MBB.begin()) {
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--I;
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if (I->isDebugValue())
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continue;
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// Working from the bottom, when we see a non-terminator instruction, we're
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// done.
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if (!isUnpredicatedTerminator(I))
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break;
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// A terminator that isn't a branch can't easily be handled by this
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// analysis.
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if (!I->isBranch())
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return true;
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// Can't handle indirect branches.
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SystemZII::Branch Branch(getBranchInfo(I));
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if (!Branch.Target->isMBB())
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return true;
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// Punt on compound branches.
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if (Branch.Type != SystemZII::BranchNormal)
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return true;
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if (Branch.CCMask == SystemZ::CCMASK_ANY) {
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// Handle unconditional branches.
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if (!AllowModify) {
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TBB = Branch.Target->getMBB();
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continue;
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}
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// If the block has any instructions after a JMP, delete them.
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while (llvm::next(I) != MBB.end())
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llvm::next(I)->eraseFromParent();
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Cond.clear();
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FBB = 0;
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// Delete the JMP if it's equivalent to a fall-through.
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if (MBB.isLayoutSuccessor(Branch.Target->getMBB())) {
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TBB = 0;
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I->eraseFromParent();
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I = MBB.end();
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continue;
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}
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// TBB is used to indicate the unconditinal destination.
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TBB = Branch.Target->getMBB();
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continue;
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}
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// Working from the bottom, handle the first conditional branch.
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if (Cond.empty()) {
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// FIXME: add X86-style branch swap
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FBB = TBB;
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TBB = Branch.Target->getMBB();
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Cond.push_back(MachineOperand::CreateImm(Branch.CCMask));
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continue;
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}
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// Handle subsequent conditional branches.
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assert(Cond.size() == 1);
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assert(TBB);
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// Only handle the case where all conditional branches branch to the same
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// destination.
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if (TBB != Branch.Target->getMBB())
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return true;
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// If the conditions are the same, we can leave them alone.
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unsigned OldCond = Cond[0].getImm();
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if (OldCond == Branch.CCMask)
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continue;
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// FIXME: Try combining conditions like X86 does. Should be easy on Z!
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}
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return false;
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}
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unsigned SystemZInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
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// Most of the code and comments here are boilerplate.
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MachineBasicBlock::iterator I = MBB.end();
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unsigned Count = 0;
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while (I != MBB.begin()) {
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--I;
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if (I->isDebugValue())
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continue;
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if (!I->isBranch())
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break;
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if (!getBranchInfo(I).Target->isMBB())
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break;
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// Remove the branch.
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I->eraseFromParent();
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I = MBB.end();
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++Count;
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}
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return Count;
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}
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unsigned
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SystemZInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
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MachineBasicBlock *FBB,
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const SmallVectorImpl<MachineOperand> &Cond,
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DebugLoc DL) const {
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// In this function we output 32-bit branches, which should always
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// have enough range. They can be shortened and relaxed by later code
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// in the pipeline, if desired.
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// Shouldn't be a fall through.
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assert(TBB && "InsertBranch must not be told to insert a fallthrough");
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assert((Cond.size() == 1 || Cond.size() == 0) &&
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"SystemZ branch conditions have one component!");
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if (Cond.empty()) {
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// Unconditional branch?
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assert(!FBB && "Unconditional branch with multiple successors!");
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BuildMI(&MBB, DL, get(SystemZ::J)).addMBB(TBB);
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return 1;
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}
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// Conditional branch.
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unsigned Count = 0;
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unsigned CC = Cond[0].getImm();
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BuildMI(&MBB, DL, get(SystemZ::BRC)).addImm(CC).addMBB(TBB);
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++Count;
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if (FBB) {
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// Two-way Conditional branch. Insert the second branch.
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BuildMI(&MBB, DL, get(SystemZ::J)).addMBB(FBB);
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++Count;
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}
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return Count;
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}
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void
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SystemZInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI, DebugLoc DL,
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unsigned DestReg, unsigned SrcReg,
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bool KillSrc) const {
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// Split 128-bit GPR moves into two 64-bit moves. This handles ADDR128 too.
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if (SystemZ::GR128BitRegClass.contains(DestReg, SrcReg)) {
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copyPhysReg(MBB, MBBI, DL, RI.getSubReg(DestReg, SystemZ::subreg_high),
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RI.getSubReg(SrcReg, SystemZ::subreg_high), KillSrc);
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copyPhysReg(MBB, MBBI, DL, RI.getSubReg(DestReg, SystemZ::subreg_low),
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RI.getSubReg(SrcReg, SystemZ::subreg_low), KillSrc);
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return;
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}
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// Everything else needs only one instruction.
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unsigned Opcode;
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if (SystemZ::GR32BitRegClass.contains(DestReg, SrcReg))
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Opcode = SystemZ::LR;
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else if (SystemZ::GR64BitRegClass.contains(DestReg, SrcReg))
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Opcode = SystemZ::LGR;
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else if (SystemZ::FP32BitRegClass.contains(DestReg, SrcReg))
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Opcode = SystemZ::LER;
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else if (SystemZ::FP64BitRegClass.contains(DestReg, SrcReg))
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Opcode = SystemZ::LDR;
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else if (SystemZ::FP128BitRegClass.contains(DestReg, SrcReg))
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Opcode = SystemZ::LXR;
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else
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llvm_unreachable("Impossible reg-to-reg copy");
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BuildMI(MBB, MBBI, DL, get(Opcode), DestReg)
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.addReg(SrcReg, getKillRegState(KillSrc));
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}
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void
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SystemZInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI,
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unsigned SrcReg, bool isKill,
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int FrameIdx,
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const TargetRegisterClass *RC,
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const TargetRegisterInfo *TRI) const {
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DebugLoc DL = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
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// Callers may expect a single instruction, so keep 128-bit moves
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// together for now and lower them after register allocation.
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unsigned LoadOpcode, StoreOpcode;
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getLoadStoreOpcodes(RC, LoadOpcode, StoreOpcode);
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addFrameReference(BuildMI(MBB, MBBI, DL, get(StoreOpcode))
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.addReg(SrcReg, getKillRegState(isKill)), FrameIdx);
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}
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void
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SystemZInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI,
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unsigned DestReg, int FrameIdx,
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const TargetRegisterClass *RC,
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const TargetRegisterInfo *TRI) const {
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DebugLoc DL = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
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// Callers may expect a single instruction, so keep 128-bit moves
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// together for now and lower them after register allocation.
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unsigned LoadOpcode, StoreOpcode;
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getLoadStoreOpcodes(RC, LoadOpcode, StoreOpcode);
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addFrameReference(BuildMI(MBB, MBBI, DL, get(LoadOpcode), DestReg),
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FrameIdx);
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}
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// Return true if MI is a simple load or store with a 12-bit displacement
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// and no index. Flag is SimpleBDXLoad for loads and SimpleBDXStore for stores.
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static bool isSimpleBD12Move(const MachineInstr *MI, unsigned Flag) {
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const MCInstrDesc &MCID = MI->getDesc();
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return ((MCID.TSFlags & Flag) &&
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isUInt<12>(MI->getOperand(2).getImm()) &&
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MI->getOperand(3).getReg() == 0);
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}
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MachineInstr *
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SystemZInstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
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MachineInstr *MI,
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const SmallVectorImpl<unsigned> &Ops,
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int FrameIndex) const {
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const MachineFrameInfo *MFI = MF.getFrameInfo();
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unsigned Size = MFI->getObjectSize(FrameIndex);
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// Eary exit for cases we don't care about
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if (Ops.size() != 1)
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return 0;
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unsigned OpNum = Ops[0];
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assert(Size == MF.getRegInfo()
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.getRegClass(MI->getOperand(OpNum).getReg())->getSize() &&
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"Invalid size combination");
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unsigned Opcode = MI->getOpcode();
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if (Opcode == SystemZ::LGDR || Opcode == SystemZ::LDGR) {
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bool Op0IsGPR = (Opcode == SystemZ::LGDR);
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bool Op1IsGPR = (Opcode == SystemZ::LDGR);
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// If we're spilling the destination of an LDGR or LGDR, store the
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// source register instead.
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if (OpNum == 0) {
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unsigned StoreOpcode = Op1IsGPR ? SystemZ::STG : SystemZ::STD;
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return BuildMI(MF, MI->getDebugLoc(), get(StoreOpcode))
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.addOperand(MI->getOperand(1)).addFrameIndex(FrameIndex)
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.addImm(0).addReg(0);
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}
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// If we're spilling the source of an LDGR or LGDR, load the
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// destination register instead.
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if (OpNum == 1) {
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unsigned LoadOpcode = Op0IsGPR ? SystemZ::LG : SystemZ::LD;
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unsigned Dest = MI->getOperand(0).getReg();
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return BuildMI(MF, MI->getDebugLoc(), get(LoadOpcode), Dest)
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.addFrameIndex(FrameIndex).addImm(0).addReg(0);
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}
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}
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// Look for cases where the source of a simple store or the destination
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// of a simple load is being spilled. Try to use MVC instead.
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//
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// Although MVC is in practice a fast choice in these cases, it is still
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// logically a bytewise copy. This means that we cannot use it if the
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// load or store is volatile. It also means that the transformation is
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// not valid in cases where the two memories partially overlap; however,
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// that is not a problem here, because we know that one of the memories
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// is a full frame index.
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if (OpNum == 0 && MI->hasOneMemOperand()) {
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MachineMemOperand *MMO = *MI->memoperands_begin();
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if (MMO->getSize() == Size && !MMO->isVolatile()) {
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// Handle conversion of loads.
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if (isSimpleBD12Move(MI, SystemZII::SimpleBDXLoad)) {
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return BuildMI(MF, MI->getDebugLoc(), get(SystemZ::MVC))
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.addFrameIndex(FrameIndex).addImm(0).addImm(Size)
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.addOperand(MI->getOperand(1)).addImm(MI->getOperand(2).getImm())
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.addMemOperand(MMO);
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}
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// Handle conversion of stores.
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if (isSimpleBD12Move(MI, SystemZII::SimpleBDXStore)) {
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return BuildMI(MF, MI->getDebugLoc(), get(SystemZ::MVC))
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.addOperand(MI->getOperand(1)).addImm(MI->getOperand(2).getImm())
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.addImm(Size).addFrameIndex(FrameIndex).addImm(0)
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.addMemOperand(MMO);
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}
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}
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}
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// If the spilled operand is the final one, try to change <INSN>R
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// into <INSN>.
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int MemOpcode = SystemZ::getMemOpcode(Opcode);
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if (MemOpcode >= 0) {
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unsigned NumOps = MI->getNumExplicitOperands();
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if (OpNum == NumOps - 1) {
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const MCInstrDesc &MemDesc = get(MemOpcode);
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uint64_t AccessBytes = SystemZII::getAccessSize(MemDesc.TSFlags);
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assert(AccessBytes != 0 && "Size of access should be known");
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assert(AccessBytes <= Size && "Access outside the frame index");
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uint64_t Offset = Size - AccessBytes;
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MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), get(MemOpcode));
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for (unsigned I = 0; I < OpNum; ++I)
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MIB.addOperand(MI->getOperand(I));
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MIB.addFrameIndex(FrameIndex).addImm(Offset);
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if (MemDesc.TSFlags & SystemZII::HasIndex)
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MIB.addReg(0);
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return MIB;
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}
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}
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return 0;
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}
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MachineInstr *
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SystemZInstrInfo::foldMemoryOperandImpl(MachineFunction &MF, MachineInstr* MI,
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const SmallVectorImpl<unsigned> &Ops,
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MachineInstr* LoadMI) const {
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return 0;
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}
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bool
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SystemZInstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const {
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switch (MI->getOpcode()) {
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case SystemZ::L128:
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splitMove(MI, SystemZ::LG);
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return true;
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case SystemZ::ST128:
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splitMove(MI, SystemZ::STG);
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return true;
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case SystemZ::LX:
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splitMove(MI, SystemZ::LD);
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return true;
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case SystemZ::STX:
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splitMove(MI, SystemZ::STD);
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return true;
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case SystemZ::ADJDYNALLOC:
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splitAdjDynAlloc(MI);
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return true;
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default:
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return false;
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}
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}
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bool SystemZInstrInfo::
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ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
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assert(Cond.size() == 1 && "Invalid branch condition!");
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Cond[0].setImm(Cond[0].getImm() ^ SystemZ::CCMASK_ANY);
|
|
return false;
|
|
}
|
|
|
|
uint64_t SystemZInstrInfo::getInstSizeInBytes(const MachineInstr *MI) const {
|
|
if (MI->getOpcode() == TargetOpcode::INLINEASM) {
|
|
const MachineFunction *MF = MI->getParent()->getParent();
|
|
const char *AsmStr = MI->getOperand(0).getSymbolName();
|
|
return getInlineAsmLength(AsmStr, *MF->getTarget().getMCAsmInfo());
|
|
}
|
|
return MI->getDesc().getSize();
|
|
}
|
|
|
|
SystemZII::Branch
|
|
SystemZInstrInfo::getBranchInfo(const MachineInstr *MI) const {
|
|
switch (MI->getOpcode()) {
|
|
case SystemZ::BR:
|
|
case SystemZ::J:
|
|
case SystemZ::JG:
|
|
return SystemZII::Branch(SystemZII::BranchNormal, SystemZ::CCMASK_ANY,
|
|
&MI->getOperand(0));
|
|
|
|
case SystemZ::BRC:
|
|
case SystemZ::BRCL:
|
|
return SystemZII::Branch(SystemZII::BranchNormal,
|
|
MI->getOperand(0).getImm(), &MI->getOperand(1));
|
|
|
|
case SystemZ::CIJ:
|
|
case SystemZ::CRJ:
|
|
return SystemZII::Branch(SystemZII::BranchC, MI->getOperand(2).getImm(),
|
|
&MI->getOperand(3));
|
|
|
|
case SystemZ::CGIJ:
|
|
case SystemZ::CGRJ:
|
|
return SystemZII::Branch(SystemZII::BranchCG, MI->getOperand(2).getImm(),
|
|
&MI->getOperand(3));
|
|
|
|
default:
|
|
llvm_unreachable("Unrecognized branch opcode");
|
|
}
|
|
}
|
|
|
|
void SystemZInstrInfo::getLoadStoreOpcodes(const TargetRegisterClass *RC,
|
|
unsigned &LoadOpcode,
|
|
unsigned &StoreOpcode) const {
|
|
if (RC == &SystemZ::GR32BitRegClass || RC == &SystemZ::ADDR32BitRegClass) {
|
|
LoadOpcode = SystemZ::L;
|
|
StoreOpcode = SystemZ::ST32;
|
|
} else if (RC == &SystemZ::GR64BitRegClass ||
|
|
RC == &SystemZ::ADDR64BitRegClass) {
|
|
LoadOpcode = SystemZ::LG;
|
|
StoreOpcode = SystemZ::STG;
|
|
} else if (RC == &SystemZ::GR128BitRegClass ||
|
|
RC == &SystemZ::ADDR128BitRegClass) {
|
|
LoadOpcode = SystemZ::L128;
|
|
StoreOpcode = SystemZ::ST128;
|
|
} else if (RC == &SystemZ::FP32BitRegClass) {
|
|
LoadOpcode = SystemZ::LE;
|
|
StoreOpcode = SystemZ::STE;
|
|
} else if (RC == &SystemZ::FP64BitRegClass) {
|
|
LoadOpcode = SystemZ::LD;
|
|
StoreOpcode = SystemZ::STD;
|
|
} else if (RC == &SystemZ::FP128BitRegClass) {
|
|
LoadOpcode = SystemZ::LX;
|
|
StoreOpcode = SystemZ::STX;
|
|
} else
|
|
llvm_unreachable("Unsupported regclass to load or store");
|
|
}
|
|
|
|
unsigned SystemZInstrInfo::getOpcodeForOffset(unsigned Opcode,
|
|
int64_t Offset) const {
|
|
const MCInstrDesc &MCID = get(Opcode);
|
|
int64_t Offset2 = (MCID.TSFlags & SystemZII::Is128Bit ? Offset + 8 : Offset);
|
|
if (isUInt<12>(Offset) && isUInt<12>(Offset2)) {
|
|
// Get the instruction to use for unsigned 12-bit displacements.
|
|
int Disp12Opcode = SystemZ::getDisp12Opcode(Opcode);
|
|
if (Disp12Opcode >= 0)
|
|
return Disp12Opcode;
|
|
|
|
// All address-related instructions can use unsigned 12-bit
|
|
// displacements.
|
|
return Opcode;
|
|
}
|
|
if (isInt<20>(Offset) && isInt<20>(Offset2)) {
|
|
// Get the instruction to use for signed 20-bit displacements.
|
|
int Disp20Opcode = SystemZ::getDisp20Opcode(Opcode);
|
|
if (Disp20Opcode >= 0)
|
|
return Disp20Opcode;
|
|
|
|
// Check whether Opcode allows signed 20-bit displacements.
|
|
if (MCID.TSFlags & SystemZII::Has20BitOffset)
|
|
return Opcode;
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
unsigned SystemZInstrInfo::getCompareAndBranch(unsigned Opcode,
|
|
const MachineInstr *MI) const {
|
|
switch (Opcode) {
|
|
case SystemZ::CR:
|
|
return SystemZ::CRJ;
|
|
case SystemZ::CGR:
|
|
return SystemZ::CGRJ;
|
|
case SystemZ::CHI:
|
|
return MI && isInt<8>(MI->getOperand(1).getImm()) ? SystemZ::CIJ : 0;
|
|
case SystemZ::CGHI:
|
|
return MI && isInt<8>(MI->getOperand(1).getImm()) ? SystemZ::CGIJ : 0;
|
|
default:
|
|
return 0;
|
|
}
|
|
}
|
|
|
|
void SystemZInstrInfo::loadImmediate(MachineBasicBlock &MBB,
|
|
MachineBasicBlock::iterator MBBI,
|
|
unsigned Reg, uint64_t Value) const {
|
|
DebugLoc DL = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
|
|
unsigned Opcode;
|
|
if (isInt<16>(Value))
|
|
Opcode = SystemZ::LGHI;
|
|
else if (SystemZ::isImmLL(Value))
|
|
Opcode = SystemZ::LLILL;
|
|
else if (SystemZ::isImmLH(Value)) {
|
|
Opcode = SystemZ::LLILH;
|
|
Value >>= 16;
|
|
} else {
|
|
assert(isInt<32>(Value) && "Huge values not handled yet");
|
|
Opcode = SystemZ::LGFI;
|
|
}
|
|
BuildMI(MBB, MBBI, DL, get(Opcode), Reg).addImm(Value);
|
|
}
|