forked from OSchip/llvm-project
204 lines
6.6 KiB
C++
204 lines
6.6 KiB
C++
//===-- RISCVAsmPrinter.cpp - RISCV LLVM assembly writer ------------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains a printer that converts from our internal representation
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// of machine-dependent LLVM code to the RISCV assembly language.
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//
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//===----------------------------------------------------------------------===//
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#include "MCTargetDesc/RISCVInstPrinter.h"
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#include "MCTargetDesc/RISCVMCExpr.h"
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#include "MCTargetDesc/RISCVTargetStreamer.h"
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#include "RISCV.h"
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#include "RISCVTargetMachine.h"
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#include "TargetInfo/RISCVTargetInfo.h"
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#include "llvm/ADT/Statistic.h"
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#include "llvm/CodeGen/AsmPrinter.h"
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#include "llvm/CodeGen/MachineConstantPool.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/MachineModuleInfo.h"
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#include "llvm/MC/MCAsmInfo.h"
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#include "llvm/MC/MCInst.h"
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#include "llvm/MC/MCStreamer.h"
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#include "llvm/MC/MCSymbol.h"
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#include "llvm/Support/TargetRegistry.h"
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#include "llvm/Support/raw_ostream.h"
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using namespace llvm;
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#define DEBUG_TYPE "asm-printer"
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STATISTIC(RISCVNumInstrsCompressed,
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"Number of RISC-V Compressed instructions emitted");
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namespace {
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class RISCVAsmPrinter : public AsmPrinter {
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const MCSubtargetInfo *STI;
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public:
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explicit RISCVAsmPrinter(TargetMachine &TM,
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std::unique_ptr<MCStreamer> Streamer)
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: AsmPrinter(TM, std::move(Streamer)), STI(TM.getMCSubtargetInfo()) {}
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StringRef getPassName() const override { return "RISCV Assembly Printer"; }
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bool runOnMachineFunction(MachineFunction &MF) override;
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void emitInstruction(const MachineInstr *MI) override;
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bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
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const char *ExtraCode, raw_ostream &OS) override;
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bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNo,
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const char *ExtraCode, raw_ostream &OS) override;
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void EmitToStreamer(MCStreamer &S, const MCInst &Inst);
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bool emitPseudoExpansionLowering(MCStreamer &OutStreamer,
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const MachineInstr *MI);
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// Wrapper needed for tblgenned pseudo lowering.
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bool lowerOperand(const MachineOperand &MO, MCOperand &MCOp) const {
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return LowerRISCVMachineOperandToMCOperand(MO, MCOp, *this);
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}
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void emitStartOfAsmFile(Module &M) override;
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void emitEndOfAsmFile(Module &M) override;
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private:
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void emitAttributes();
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};
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}
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#define GEN_COMPRESS_INSTR
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#include "RISCVGenCompressInstEmitter.inc"
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void RISCVAsmPrinter::EmitToStreamer(MCStreamer &S, const MCInst &Inst) {
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MCInst CInst;
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bool Res = compressInst(CInst, Inst, *STI, OutStreamer->getContext());
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if (Res)
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++RISCVNumInstrsCompressed;
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AsmPrinter::EmitToStreamer(*OutStreamer, Res ? CInst : Inst);
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}
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// Simple pseudo-instructions have their lowering (with expansion to real
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// instructions) auto-generated.
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#include "RISCVGenMCPseudoLowering.inc"
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void RISCVAsmPrinter::emitInstruction(const MachineInstr *MI) {
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// Do any auto-generated pseudo lowerings.
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if (emitPseudoExpansionLowering(*OutStreamer, MI))
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return;
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MCInst TmpInst;
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if (!lowerRISCVMachineInstrToMCInst(MI, TmpInst, *this))
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EmitToStreamer(*OutStreamer, TmpInst);
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}
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bool RISCVAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
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const char *ExtraCode, raw_ostream &OS) {
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// First try the generic code, which knows about modifiers like 'c' and 'n'.
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if (!AsmPrinter::PrintAsmOperand(MI, OpNo, ExtraCode, OS))
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return false;
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const MachineOperand &MO = MI->getOperand(OpNo);
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if (ExtraCode && ExtraCode[0]) {
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if (ExtraCode[1] != 0)
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return true; // Unknown modifier.
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switch (ExtraCode[0]) {
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default:
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return true; // Unknown modifier.
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case 'z': // Print zero register if zero, regular printing otherwise.
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if (MO.isImm() && MO.getImm() == 0) {
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OS << RISCVInstPrinter::getRegisterName(RISCV::X0);
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return false;
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}
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break;
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case 'i': // Literal 'i' if operand is not a register.
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if (!MO.isReg())
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OS << 'i';
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return false;
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}
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}
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switch (MO.getType()) {
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case MachineOperand::MO_Immediate:
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OS << MO.getImm();
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return false;
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case MachineOperand::MO_Register:
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OS << RISCVInstPrinter::getRegisterName(MO.getReg());
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return false;
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case MachineOperand::MO_GlobalAddress:
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PrintSymbolOperand(MO, OS);
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return false;
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case MachineOperand::MO_BlockAddress: {
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MCSymbol *Sym = GetBlockAddressSymbol(MO.getBlockAddress());
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Sym->print(OS, MAI);
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return false;
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}
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default:
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break;
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}
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return true;
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}
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bool RISCVAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
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unsigned OpNo,
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const char *ExtraCode,
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raw_ostream &OS) {
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if (!ExtraCode) {
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const MachineOperand &MO = MI->getOperand(OpNo);
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// For now, we only support register memory operands in registers and
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// assume there is no addend
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if (!MO.isReg())
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return true;
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OS << "0(" << RISCVInstPrinter::getRegisterName(MO.getReg()) << ")";
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return false;
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}
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return AsmPrinter::PrintAsmMemoryOperand(MI, OpNo, ExtraCode, OS);
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}
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bool RISCVAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
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// Set the current MCSubtargetInfo to a copy which has the correct
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// feature bits for the current MachineFunction
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MCSubtargetInfo &NewSTI =
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OutStreamer->getContext().getSubtargetCopy(*TM.getMCSubtargetInfo());
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NewSTI.setFeatureBits(MF.getSubtarget().getFeatureBits());
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STI = &NewSTI;
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SetupMachineFunction(MF);
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emitFunctionBody();
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return false;
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}
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void RISCVAsmPrinter::emitStartOfAsmFile(Module &M) {
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if (TM.getTargetTriple().isOSBinFormatELF())
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emitAttributes();
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}
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void RISCVAsmPrinter::emitEndOfAsmFile(Module &M) {
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RISCVTargetStreamer &RTS =
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static_cast<RISCVTargetStreamer &>(*OutStreamer->getTargetStreamer());
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if (TM.getTargetTriple().isOSBinFormatELF())
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RTS.finishAttributeSection();
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}
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void RISCVAsmPrinter::emitAttributes() {
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RISCVTargetStreamer &RTS =
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static_cast<RISCVTargetStreamer &>(*OutStreamer->getTargetStreamer());
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RTS.emitTargetAttributes(*STI);
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}
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// Force static initialization.
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extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeRISCVAsmPrinter() {
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RegisterAsmPrinter<RISCVAsmPrinter> X(getTheRISCV32Target());
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RegisterAsmPrinter<RISCVAsmPrinter> Y(getTheRISCV64Target());
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}
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