forked from OSchip/llvm-project
299 lines
13 KiB
TableGen
299 lines
13 KiB
TableGen
//===-- RISCV.td - Describe the RISCV Target Machine -------*- tablegen -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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include "llvm/Target/Target.td"
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//===----------------------------------------------------------------------===//
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// RISC-V subtarget features and instruction predicates.
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//===----------------------------------------------------------------------===//
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def FeatureStdExtM
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: SubtargetFeature<"m", "HasStdExtM", "true",
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"'M' (Integer Multiplication and Division)">;
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def HasStdExtM : Predicate<"Subtarget->hasStdExtM()">,
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AssemblerPredicate<(all_of FeatureStdExtM),
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"'M' (Integer Multiplication and Division)">;
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def FeatureStdExtA
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: SubtargetFeature<"a", "HasStdExtA", "true",
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"'A' (Atomic Instructions)">;
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def HasStdExtA : Predicate<"Subtarget->hasStdExtA()">,
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AssemblerPredicate<(all_of FeatureStdExtA),
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"'A' (Atomic Instructions)">;
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def FeatureStdExtF
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: SubtargetFeature<"f", "HasStdExtF", "true",
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"'F' (Single-Precision Floating-Point)">;
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def HasStdExtF : Predicate<"Subtarget->hasStdExtF()">,
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AssemblerPredicate<(all_of FeatureStdExtF),
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"'F' (Single-Precision Floating-Point)">;
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def FeatureStdExtD
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: SubtargetFeature<"d", "HasStdExtD", "true",
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"'D' (Double-Precision Floating-Point)",
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[FeatureStdExtF]>;
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def HasStdExtD : Predicate<"Subtarget->hasStdExtD()">,
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AssemblerPredicate<(all_of FeatureStdExtD),
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"'D' (Double-Precision Floating-Point)">;
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def FeatureExtZfh
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: SubtargetFeature<"experimental-zfh", "HasStdExtZfh", "true",
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"'Zfh' (Half-Precision Floating-Point)",
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[FeatureStdExtF]>;
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def HasStdExtZfh : Predicate<"Subtarget->hasStdExtZfh()">,
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AssemblerPredicate<(all_of FeatureExtZfh),
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"'Zfh' (Half-Precision Floating-Point)">;
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def FeatureStdExtC
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: SubtargetFeature<"c", "HasStdExtC", "true",
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"'C' (Compressed Instructions)">;
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def HasStdExtC : Predicate<"Subtarget->hasStdExtC()">,
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AssemblerPredicate<(all_of FeatureStdExtC),
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"'C' (Compressed Instructions)">;
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def FeatureExtZba
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: SubtargetFeature<"experimental-zba", "HasStdExtZba", "true",
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"'Zba' (Address calculation 'B' Instructions)">;
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def HasStdExtZba : Predicate<"Subtarget->hasStdExtZba()">,
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AssemblerPredicate<(all_of FeatureExtZba),
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"'Zba' (Address calculation 'B' Instructions)">;
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def NotHasStdExtZba : Predicate<"!Subtarget->hasStdExtZba()">;
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def FeatureExtZbb
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: SubtargetFeature<"experimental-zbb", "HasStdExtZbb", "true",
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"'Zbb' (Base 'B' Instructions)">;
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def HasStdExtZbb : Predicate<"Subtarget->hasStdExtZbb()">,
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AssemblerPredicate<(all_of FeatureExtZbb),
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"'Zbb' (Base 'B' Instructions)">;
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def FeatureExtZbc
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: SubtargetFeature<"experimental-zbc", "HasStdExtZbc", "true",
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"'Zbc' (Carry-Less 'B' Instructions)">;
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def HasStdExtZbc : Predicate<"Subtarget->hasStdExtZbc()">,
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AssemblerPredicate<(all_of FeatureExtZbc),
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"'Zbc' (Carry-Less 'B' Instructions)">;
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def FeatureExtZbe
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: SubtargetFeature<"experimental-zbe", "HasStdExtZbe", "true",
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"'Zbe' (Extract-Deposit 'B' Instructions)">;
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def HasStdExtZbe : Predicate<"Subtarget->hasStdExtZbe()">,
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AssemblerPredicate<(all_of FeatureExtZbe),
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"'Zbe' (Extract-Deposit 'B' Instructions)">;
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def FeatureExtZbf
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: SubtargetFeature<"experimental-zbf", "HasStdExtZbf", "true",
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"'Zbf' (Bit-Field 'B' Instructions)">;
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def HasStdExtZbf : Predicate<"Subtarget->hasStdExtZbf()">,
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AssemblerPredicate<(all_of FeatureExtZbf),
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"'Zbf' (Bit-Field 'B' Instructions)">;
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def FeatureExtZbm
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: SubtargetFeature<"experimental-zbm", "HasStdExtZbm", "true",
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"'Zbm' (Matrix 'B' Instructions)">;
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def HasStdExtZbm : Predicate<"Subtarget->hasStdExtZbm()">,
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AssemblerPredicate<(all_of FeatureExtZbm),
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"'Zbm' (Matrix 'B' Instructions)">;
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def FeatureExtZbp
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: SubtargetFeature<"experimental-zbp", "HasStdExtZbp", "true",
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"'Zbp' (Permutation 'B' Instructions)">;
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def HasStdExtZbp : Predicate<"Subtarget->hasStdExtZbp()">,
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AssemblerPredicate<(all_of FeatureExtZbp),
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"'Zbp' (Permutation 'B' Instructions)">;
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def FeatureExtZbr
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: SubtargetFeature<"experimental-zbr", "HasStdExtZbr", "true",
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"'Zbr' (Polynomial Reduction 'B' Instructions)">;
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def HasStdExtZbr : Predicate<"Subtarget->hasStdExtZbr()">,
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AssemblerPredicate<(all_of FeatureExtZbr),
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"'Zbr' (Polynomial Reduction 'B' Instructions)">;
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def FeatureExtZbs
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: SubtargetFeature<"experimental-zbs", "HasStdExtZbs", "true",
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"'Zbs' (Single-Bit 'B' Instructions)">;
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def HasStdExtZbs : Predicate<"Subtarget->hasStdExtZbs()">,
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AssemblerPredicate<(all_of FeatureExtZbs),
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"'Zbs' (Single-Bit 'B' Instructions)">;
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def FeatureExtZbt
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: SubtargetFeature<"experimental-zbt", "HasStdExtZbt", "true",
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"'Zbt' (Ternary 'B' Instructions)">;
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def HasStdExtZbt : Predicate<"Subtarget->hasStdExtZbt()">,
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AssemblerPredicate<(all_of FeatureExtZbt),
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"'Zbt' (Ternary 'B' Instructions)">;
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// Some instructions belong to both the basic and the permutation
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// subextensions. They should be enabled if either has been specified.
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def HasStdExtZbbOrZbp
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: Predicate<"Subtarget->hasStdExtZbb() || Subtarget->hasStdExtZbp()">,
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AssemblerPredicate<(any_of FeatureExtZbb, FeatureExtZbp),
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"'Zbb' (Base 'B' Instructions) or "
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"'Zbp' (Permutation 'B' Instructions)">;
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def FeatureExtZbproposedc
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: SubtargetFeature<"experimental-zbproposedc", "HasStdExtZbproposedc", "true",
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"'Zbproposedc' (Proposed Compressed 'B' Instructions)">;
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def HasStdExtZbproposedc : Predicate<"Subtarget->hasStdExtZbproposedc()">,
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AssemblerPredicate<(all_of FeatureExtZbproposedc),
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"'Zbproposedc' (Proposed Compressed 'B' Instructions)">;
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def FeatureStdExtB
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: SubtargetFeature<"experimental-b", "HasStdExtB", "true",
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"'B' (Bit Manipulation Instructions)",
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[FeatureExtZba,
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FeatureExtZbb,
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FeatureExtZbc,
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FeatureExtZbe,
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FeatureExtZbf,
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FeatureExtZbm,
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FeatureExtZbp,
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FeatureExtZbr,
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FeatureExtZbs,
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FeatureExtZbt]>;
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def HasStdExtB : Predicate<"Subtarget->hasStdExtB()">,
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AssemblerPredicate<(all_of FeatureStdExtB),
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"'B' (Bit Manipulation Instructions)">;
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def FeatureNoRVCHints
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: SubtargetFeature<"no-rvc-hints", "EnableRVCHintInstrs", "false",
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"Disable RVC Hint Instructions.">;
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def HasRVCHints : Predicate<"Subtarget->enableRVCHintInstrs()">,
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AssemblerPredicate<(all_of(not FeatureNoRVCHints)),
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"RVC Hint Instructions">;
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def FeatureStdExtV
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: SubtargetFeature<"experimental-v", "HasStdExtV", "true",
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"'V' (Vector Instructions)">;
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def HasStdExtV : Predicate<"Subtarget->hasStdExtV()">,
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AssemblerPredicate<(all_of FeatureStdExtV),
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"'V' (Vector Instructions)">;
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def FeatureStdExtZvlsseg
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: SubtargetFeature<"experimental-zvlsseg", "HasStdExtZvlsseg", "true",
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"'Zvlsseg' (Vector segment load/store instructions)",
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[FeatureStdExtV]>;
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def HasStdExtZvlsseg : Predicate<"Subtarget->hasStdExtZvlsseg()">,
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AssemblerPredicate<(all_of FeatureStdExtZvlsseg),
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"'Zvlsseg' (Vector segment load/store instructions)">;
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def FeatureExtZvamo
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: SubtargetFeature<"experimental-zvamo", "HasStdExtZvamo", "true",
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"'Zvamo' (Vector AMO Operations)",
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[FeatureStdExtV]>;
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def HasStdExtZvamo : Predicate<"Subtarget->hasStdExtZvamo()">,
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AssemblerPredicate<(all_of FeatureExtZvamo),
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"'Zvamo' (Vector AMO Operations)">;
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def Feature64Bit
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: SubtargetFeature<"64bit", "HasRV64", "true", "Implements RV64">;
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def IsRV64 : Predicate<"Subtarget->is64Bit()">,
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AssemblerPredicate<(all_of Feature64Bit),
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"RV64I Base Instruction Set">;
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def IsRV32 : Predicate<"!Subtarget->is64Bit()">,
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AssemblerPredicate<(all_of (not Feature64Bit)),
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"RV32I Base Instruction Set">;
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defvar RV32 = DefaultMode;
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def RV64 : HwMode<"+64bit">;
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def FeatureRV32E
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: SubtargetFeature<"e", "IsRV32E", "true",
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"Implements RV32E (provides 16 rather than 32 GPRs)">;
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def IsRV32E : Predicate<"Subtarget->isRV32E()">,
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AssemblerPredicate<(all_of FeatureRV32E)>;
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def FeatureRelax
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: SubtargetFeature<"relax", "EnableLinkerRelax", "true",
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"Enable Linker relaxation.">;
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foreach i = {1-31} in
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def FeatureReserveX#i :
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SubtargetFeature<"reserve-x"#i, "UserReservedRegister[RISCV::X"#i#"]",
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"true", "Reserve X"#i>;
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def FeatureSaveRestore : SubtargetFeature<"save-restore", "EnableSaveRestore",
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"true", "Enable save/restore.">;
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//===----------------------------------------------------------------------===//
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// Named operands for CSR instructions.
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//===----------------------------------------------------------------------===//
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include "RISCVSystemOperands.td"
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//===----------------------------------------------------------------------===//
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// Registers, calling conventions, instruction descriptions.
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//===----------------------------------------------------------------------===//
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include "RISCVSchedule.td"
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include "RISCVRegisterInfo.td"
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include "RISCVCallingConv.td"
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include "RISCVInstrInfo.td"
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include "RISCVRegisterBanks.td"
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include "RISCVSchedRocket.td"
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include "RISCVSchedSiFive7.td"
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//===----------------------------------------------------------------------===//
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// RISC-V processors supported.
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//===----------------------------------------------------------------------===//
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def : ProcessorModel<"generic-rv32", NoSchedModel, []>;
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def : ProcessorModel<"generic-rv64", NoSchedModel, [Feature64Bit]>;
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def : ProcessorModel<"rocket-rv32", RocketModel, []>;
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def : ProcessorModel<"rocket-rv64", RocketModel, [Feature64Bit]>;
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def : ProcessorModel<"sifive-7-rv32", SiFive7Model, []>;
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def : ProcessorModel<"sifive-7-rv64", SiFive7Model, [Feature64Bit]>;
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def : ProcessorModel<"sifive-e31", RocketModel, [FeatureStdExtM,
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FeatureStdExtA,
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FeatureStdExtC]>;
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def : ProcessorModel<"sifive-u54", RocketModel, [Feature64Bit,
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FeatureStdExtM,
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FeatureStdExtA,
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FeatureStdExtF,
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FeatureStdExtD,
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FeatureStdExtC]>;
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def : ProcessorModel<"sifive-e76", SiFive7Model, [FeatureStdExtM,
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FeatureStdExtA,
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FeatureStdExtF,
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FeatureStdExtC]>;
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def : ProcessorModel<"sifive-u74", SiFive7Model, [Feature64Bit,
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FeatureStdExtM,
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FeatureStdExtA,
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FeatureStdExtF,
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FeatureStdExtD,
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FeatureStdExtC]>;
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//===----------------------------------------------------------------------===//
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// Define the RISC-V target.
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//===----------------------------------------------------------------------===//
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def RISCVInstrInfo : InstrInfo {
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let guessInstructionProperties = 0;
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}
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def RISCVAsmParser : AsmParser {
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let ShouldEmitMatchRegisterAltName = 1;
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let AllowDuplicateRegisterNames = 1;
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}
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def RISCVAsmWriter : AsmWriter {
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int PassSubtarget = 1;
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}
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def RISCV : Target {
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let InstructionSet = RISCVInstrInfo;
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let AssemblyParsers = [RISCVAsmParser];
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let AssemblyWriters = [RISCVAsmWriter];
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let AllowRegisterRenaming = 1;
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}
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