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AsmParser
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Revert "Use ManagedStatic and lazy initialization of cl::opt in libSupport to make it free of global initializer"
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2021-07-16 03:46:53 +00:00 |
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Disassembler
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[RISCV] Fix shared libs build
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2021-02-09 06:14:25 -06:00 |
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MCTargetDesc
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[RISCV] Pass FeatureBitset by reference rather than by value. NFCI
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2021-07-04 23:11:40 -07:00 |
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TargetInfo
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CMakeLists.txt
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[RISCV] Add a vsetvli insert pass that can be extended to be aware of incoming VL/VTYPE from other basic blocks.
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2021-05-24 11:47:27 -07:00 |
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RISCV.h
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[RISCV] Add a vsetvli insert pass that can be extended to be aware of incoming VL/VTYPE from other basic blocks.
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2021-05-24 11:47:27 -07:00 |
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RISCV.td
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[RISCV][NFC] Fix formatting
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2021-04-09 14:41:09 +08:00 |
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RISCVAsmPrinter.cpp
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[RISCV][NFC] Don't need to create a new STI in RISCVAsmPrinter.
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2021-05-10 09:33:23 +08:00 |
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RISCVCallLowering.cpp
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RISCVCallLowering.h
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RISCVCallingConv.td
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RISCVExpandAtomicPseudoInsts.cpp
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RISCVExpandPseudoInsts.cpp
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[RISCV] Add a vsetvli insert pass that can be extended to be aware of incoming VL/VTYPE from other basic blocks.
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2021-05-24 11:47:27 -07:00 |
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RISCVFrameLowering.cpp
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[RISCV] Avoid scalar outgoing argumetns overwriting vector frame objects.
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2021-06-11 12:26:29 +08:00 |
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RISCVFrameLowering.h
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[RISCV] Fix offset computation for RVV
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2021-03-29 17:03:49 +00:00 |
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RISCVISelDAGToDAG.cpp
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[RISCV] Add explicit copy to V0 in the masked vmsge(u).vx intrinsic handling.
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2021-06-23 08:04:42 -07:00 |
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RISCVISelDAGToDAG.h
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[RISCV] Use bitfields to shrink the size of the vector load/store intrinsics to pseudo instruction lookup tables.
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2021-06-07 17:57:51 -07:00 |
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RISCVISelLowering.cpp
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[RISCV] Fix the neutral element in vector 'fadd' reductions
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2021-07-14 10:18:38 +01:00 |
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RISCVISelLowering.h
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[RISCV] Add support for matching vwmul(u) and vwmacc(u) from fixed vectors.
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2021-07-06 10:24:31 -07:00 |
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RISCVInsertVSETVLI.cpp
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[RISCV] Remove extra character from a comment. NFC
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2021-06-21 12:52:02 -07:00 |
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RISCVInstrFormats.td
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[RISCV] Cleanup instruction formats used for B extension ternary operations.
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2021-05-06 08:59:05 -07:00 |
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RISCVInstrFormatsC.td
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RISCVInstrFormatsV.td
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RISCVInstrInfo.cpp
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[RISCV] Permit larger RVV stacks and stack offsets
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2021-06-25 07:17:33 +01:00 |
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RISCVInstrInfo.h
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Further improve register allocation for vwadd(u).wv, vwsub(u).wv, vfwadd.wv, and vfwsub.wv.
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2021-06-08 09:43:43 -07:00 |
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RISCVInstrInfo.td
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[RISCV] Prevent use of t0(aka x5) as rs1 for jalr instructions.
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2021-07-13 09:46:21 -07:00 |
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RISCVInstrInfoA.td
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[RISCV][NFC] Add explicit type i64 to RV64 only patterns.
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2021-04-09 09:37:04 +08:00 |
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RISCVInstrInfoB.td
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[RISCV] Prevent formation of shXadd(.uw) and add.uw if it prevents the use of addi.
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2021-06-19 12:10:42 -07:00 |
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RISCVInstrInfoC.td
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[RISCV] Rename WriteShift/ReadShift scheduler classes to WriteShiftImm/ReadShiftImm. Move variable shifts from WriteIALU/ReadIALU to new WriteShiftReg/ReadShiftReg.
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2021-03-19 20:39:49 -07:00 |
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RISCVInstrInfoD.td
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[RISCV] Implement lround*/llround*/lrint*/llrint* with fcvt instruction with -fno-math-errno
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2021-07-06 11:43:22 -07:00 |
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RISCVInstrInfoF.td
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[RISCV] Implement lround*/llround*/lrint*/llrint* with fcvt instruction with -fno-math-errno
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2021-07-06 11:43:22 -07:00 |
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RISCVInstrInfoM.td
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[RISCV] Add custom type legalization to form MULHSU when possible.
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2021-04-01 10:15:55 -07:00 |
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RISCVInstrInfoV.td
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[RISCV] Temporary in vmsge(u).vx pseudo instructions can't be V0.
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2021-04-21 14:50:29 -07:00 |
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RISCVInstrInfoVPseudos.td
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[RISCV] Add isel patterns to match vmacc/vmadd/vnmsub/vnmsac from add/sub and mul.
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2021-06-21 11:27:44 -07:00 |
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RISCVInstrInfoVSDPatterns.td
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[RISCV] Add isel patterns to match vmacc/vmadd/vnmsub/vnmsac from add/sub and mul.
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2021-06-21 11:27:44 -07:00 |
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RISCVInstrInfoVVLPatterns.td
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[RISCV] Add support for matching vwmul(u) and vwmacc(u) from fixed vectors.
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2021-07-06 10:24:31 -07:00 |
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RISCVInstrInfoZfh.td
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[RISCV] Implement lround*/llround*/lrint*/llrint* with fcvt instruction with -fno-math-errno
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2021-07-06 11:43:22 -07:00 |
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RISCVInstructionSelector.cpp
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RISCVLegalizerInfo.cpp
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[globalisel][legalizer] Separate the deprecated LegalizerInfo from the current one
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2021-06-01 13:23:48 -07:00 |
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RISCVLegalizerInfo.h
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RISCVMCInstLower.cpp
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[RISCV] Move instruction information into the RISCVII namespace (NFC)
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2021-05-11 16:32:42 -05:00 |
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RISCVMachineFunctionInfo.h
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[RISCV] Don't emit save-restore call if function is a interrupt handler
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2021-04-16 12:54:47 +08:00 |
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RISCVMergeBaseOffset.cpp
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RISCVRegisterBankInfo.cpp
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RISCVRegisterBankInfo.h
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RISCVRegisterBanks.td
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RISCVRegisterInfo.cpp
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[RISCV] Reserve an emergency spill slot for any RVV spills
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2021-06-03 10:44:34 +01:00 |
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RISCVRegisterInfo.h
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[RISCV] Improve register allocation around vector masks
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2021-02-20 14:47:51 +00:00 |
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RISCVRegisterInfo.td
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[RISCV] Prevent use of t0(aka x5) as rs1 for jalr instructions.
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2021-07-13 09:46:21 -07:00 |
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RISCVSchedRocket.td
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[RISCV] Add UnsupportedSchedZfh multiclass to reduce duplicate lines from RISCVSchedRocket.td and RISCVSchedSiFive7.td. NFC
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2021-03-31 15:06:14 -07:00 |
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RISCVSchedSiFive7.td
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[RISCV] Add UnsupportedSchedZfh multiclass to reduce duplicate lines from RISCVSchedRocket.td and RISCVSchedSiFive7.td. NFC
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2021-03-31 15:06:14 -07:00 |
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RISCVSchedule.td
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[RISCV] Add UnsupportedSchedZfh multiclass to reduce duplicate lines from RISCVSchedRocket.td and RISCVSchedSiFive7.td. NFC
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2021-03-31 15:06:14 -07:00 |
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RISCVScheduleB.td
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[RISCV] Move scheduling resources for B into a separate file (NFC)
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2021-03-29 20:37:22 -05:00 |
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RISCVSubtarget.cpp
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[RISCV] Move getLMULForFixedLengthVector out of RISCVSubtarget.
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2021-04-23 15:06:20 -07:00 |
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RISCVSubtarget.h
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[RISCV] Don't enable loop vectorizer interleaving if the V extension isn't enabled.
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2021-06-07 10:20:59 -07:00 |
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RISCVSystemOperands.td
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RISCV: add a few deprecated aliases for CSRs
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2021-05-21 13:52:58 -07:00 |
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RISCVTargetMachine.cpp
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[RISCV] Add a vsetvli insert pass that can be extended to be aware of incoming VL/VTYPE from other basic blocks.
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2021-05-24 11:47:27 -07:00 |
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RISCVTargetMachine.h
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RISCVTargetObjectFile.cpp
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ELF: Create unique SHF_GNU_RETAIN sections for llvm.used global objects
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2021-02-26 16:38:44 -08:00 |
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RISCVTargetObjectFile.h
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RISCVTargetTransformInfo.cpp
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[RISCV] Add support for fmin/fmax vector reductions
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2021-05-03 10:33:51 +01:00 |
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RISCVTargetTransformInfo.h
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[RISCV] Don't enable Interleaved Access Vectorization
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2021-06-18 12:32:30 +08:00 |
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