forked from OSchip/llvm-project
114 lines
3.9 KiB
C++
114 lines
3.9 KiB
C++
//===-- LanaiTargetMachine.cpp - Define TargetMachine for Lanai ---------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// Implements the info about Lanai target spec.
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//
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//===----------------------------------------------------------------------===//
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#include "LanaiTargetMachine.h"
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#include "Lanai.h"
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#include "LanaiTargetObjectFile.h"
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#include "LanaiTargetTransformInfo.h"
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#include "TargetInfo/LanaiTargetInfo.h"
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#include "llvm/Analysis/TargetTransformInfo.h"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
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#include "llvm/CodeGen/TargetPassConfig.h"
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#include "llvm/Support/FormattedStream.h"
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#include "llvm/Support/TargetRegistry.h"
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#include "llvm/Target/TargetOptions.h"
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using namespace llvm;
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namespace llvm {
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void initializeLanaiMemAluCombinerPass(PassRegistry &);
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} // namespace llvm
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extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeLanaiTarget() {
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// Register the target.
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RegisterTargetMachine<LanaiTargetMachine> registered_target(
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getTheLanaiTarget());
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}
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static std::string computeDataLayout() {
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// Data layout (keep in sync with clang/lib/Basic/Targets.cpp)
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return "E" // Big endian
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"-m:e" // ELF name manging
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"-p:32:32" // 32-bit pointers, 32 bit aligned
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"-i64:64" // 64 bit integers, 64 bit aligned
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"-a:0:32" // 32 bit alignment of objects of aggregate type
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"-n32" // 32 bit native integer width
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"-S64"; // 64 bit natural stack alignment
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}
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static Reloc::Model getEffectiveRelocModel(Optional<Reloc::Model> RM) {
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return RM.getValueOr(Reloc::PIC_);
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}
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LanaiTargetMachine::LanaiTargetMachine(const Target &T, const Triple &TT,
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StringRef Cpu, StringRef FeatureString,
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const TargetOptions &Options,
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Optional<Reloc::Model> RM,
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Optional<CodeModel::Model> CodeModel,
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CodeGenOpt::Level OptLevel, bool JIT)
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: LLVMTargetMachine(T, computeDataLayout(), TT, Cpu, FeatureString, Options,
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getEffectiveRelocModel(RM),
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getEffectiveCodeModel(CodeModel, CodeModel::Medium),
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OptLevel),
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Subtarget(TT, Cpu, FeatureString, *this, Options, getCodeModel(),
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OptLevel),
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TLOF(new LanaiTargetObjectFile()) {
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initAsmInfo();
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}
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TargetTransformInfo
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LanaiTargetMachine::getTargetTransformInfo(const Function &F) {
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return TargetTransformInfo(LanaiTTIImpl(this, F));
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}
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namespace {
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// Lanai Code Generator Pass Configuration Options.
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class LanaiPassConfig : public TargetPassConfig {
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public:
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LanaiPassConfig(LanaiTargetMachine &TM, PassManagerBase *PassManager)
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: TargetPassConfig(TM, *PassManager) {}
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LanaiTargetMachine &getLanaiTargetMachine() const {
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return getTM<LanaiTargetMachine>();
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}
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bool addInstSelector() override;
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void addPreSched2() override;
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void addPreEmitPass() override;
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};
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} // namespace
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TargetPassConfig *
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LanaiTargetMachine::createPassConfig(PassManagerBase &PassManager) {
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return new LanaiPassConfig(*this, &PassManager);
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}
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// Install an instruction selector pass.
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bool LanaiPassConfig::addInstSelector() {
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addPass(createLanaiISelDag(getLanaiTargetMachine()));
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return false;
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}
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// Implemented by targets that want to run passes immediately before
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// machine code is emitted.
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void LanaiPassConfig::addPreEmitPass() {
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addPass(createLanaiDelaySlotFillerPass(getLanaiTargetMachine()));
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}
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// Run passes after prolog-epilog insertion and before the second instruction
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// scheduling pass.
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void LanaiPassConfig::addPreSched2() {
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addPass(createLanaiMemAluCombinerPass());
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}
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