| .. |
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AsmParser
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[AMDGPU] Add 224-bit vector types and link 192-bit types to MVTs
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2021-06-24 12:41:22 +09:00 |
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Disassembler
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[AMDGPU] Add v5f32/VReg_160 support for MIMG instructions
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2021-06-08 11:11:40 +09:00 |
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MCTargetDesc
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[AMDGPU] Handle s_branch to another section.
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2021-07-13 12:17:47 +01:00 |
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TargetInfo
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llvmbuildectomy - replace llvm-build by plain cmake
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2020-11-13 10:35:24 +01:00 |
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Utils
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[AMDGPU] Set optional PAL metadata
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2021-07-06 11:58:00 +02:00 |
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AMDGPU.h
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[AMDGPU] Add S_MOV_B64_IMM_PSEUDO for wide constants
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2021-06-30 11:45:38 -07:00 |
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AMDGPU.td
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[AMDGPU] Removed unused Predicate HasOffset3fBug. NFC.
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2021-06-25 16:58:44 +01:00 |
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AMDGPUAliasAnalysis.cpp
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[NFC][AA] Prepare to convert AliasResult to class with PartialAlias offset.
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2021-04-09 12:54:22 +03:00 |
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AMDGPUAliasAnalysis.h
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[NFC][AMDGPU] Reduce include files dependency.
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2021-01-07 22:22:05 +03:00 |
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AMDGPUAlwaysInlinePass.cpp
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[AMDGPU] Disable forceful inline of non-kernel functions which use LDS.
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2021-04-15 09:12:56 +05:30 |
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AMDGPUAnnotateKernelFeatures.cpp
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[AMDGPU] Do not annotate features for graphics
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2021-05-03 10:33:11 +02:00 |
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AMDGPUAnnotateUniformValues.cpp
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[OpaquePtr] Clean up some uses of Type::getPointerElementType()
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2021-05-31 09:54:57 -07:00 |
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AMDGPUArgumentUsageInfo.cpp
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[GlobalISel] NFC: Change LLT::vector to take ElementCount.
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2021-06-24 11:26:12 +01:00 |
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AMDGPUArgumentUsageInfo.h
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[AMDGPU] gfx90a support
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2021-02-17 16:01:32 -08:00 |
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AMDGPUAsmPrinter.cpp
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[AMDGPU] Set optional PAL metadata
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2021-07-06 11:58:00 +02:00 |
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AMDGPUAsmPrinter.h
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[AMDGPU][IndirectCalls] Fix register usage propagation for indirect/external calls
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2021-06-12 11:59:34 +05:30 |
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AMDGPUAtomicOptimizer.cpp
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[AMDGPU] Use reductions instead of scans in the atomic optimizer
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2021-03-26 15:38:14 +00:00 |
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AMDGPUCallLowering.cpp
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GlobalISel: Track original argument index in ArgInfo
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2021-07-08 13:39:02 -04:00 |
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AMDGPUCallLowering.h
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AMDGPU/GlobalISel: Implement tail calls
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2021-05-13 18:57:42 -04:00 |
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AMDGPUCallingConv.td
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AMDGPU: Promote signext/zeroext i16 shader returns
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2021-07-13 11:04:51 -04:00 |
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AMDGPUCodeGenPrepare.cpp
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[AMDGPU] [CodeGen] Fold negate llvm.amdgcn.class into test mask
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2021-06-18 13:04:12 -06:00 |
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AMDGPUCombine.td
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AMDGPU/GlobalISel: Remove redundant G_FCANONICALIZE
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2021-04-27 12:26:37 +02:00 |
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AMDGPUExportClustering.cpp
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[AMDGPU][MC] Refactored exp tgt handling
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2021-01-26 14:54:15 +03:00 |
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AMDGPUExportClustering.h
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[llvm] Add missing header guards (NFC)
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2021-01-30 09:53:42 -08:00 |
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AMDGPUFeatures.td
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…
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AMDGPUFixFunctionBitcasts.cpp
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…
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AMDGPUFrameLowering.cpp
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…
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AMDGPUFrameLowering.h
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…
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AMDGPUGISel.td
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AMDGPU/GlobalISel: Add integer med3 combines
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2021-04-27 11:52:23 +02:00 |
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AMDGPUGenRegisterBankInfo.def
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AMDGPU/GlobalISel: Fix missing 256-bit AGPR mapping
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2020-08-17 09:53:26 -04:00 |
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AMDGPUGlobalISelUtils.cpp
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[AMDGPU][GlobalISel] Handle G_PTR_ADD when looking for constant offset
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2021-01-28 11:20:09 +01:00 |
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AMDGPUGlobalISelUtils.h
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[ADT] Move DenseMapInfo for ArrayRef/StringRef into respective headers (NFC)
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2021-06-03 18:34:36 +02:00 |
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AMDGPUHSAMetadataStreamer.cpp
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AMDGPU: Add target id and code object v4 support
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2021-03-24 11:54:05 -04:00 |
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AMDGPUHSAMetadataStreamer.h
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AMDGPU: Add target id and code object v4 support
|
2021-03-24 11:54:05 -04:00 |
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AMDGPUISelDAGToDAG.cpp
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AMDGPU: Fix high 16-bit optimization on gfx9
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2021-06-22 13:16:45 -04:00 |
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AMDGPUISelLowering.cpp
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[AMDGPU] Stop mulhi from doing 24 bit mul for uniform values
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2021-07-05 10:33:23 +01:00 |
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AMDGPUISelLowering.h
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[AMDGPU][GlobalISel] Legalize and select G_SBFX and G_UBFX
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2021-06-28 09:06:44 -04:00 |
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AMDGPUInstCombineIntrinsic.cpp
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[NFC][AMDGPU] Split AMDGPUSubtarget.h to R600 and GCN subtargets
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2021-01-20 22:22:45 +03:00 |
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AMDGPUInstrInfo.cpp
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[NFC][AMDGPU] Reduce include files dependency.
|
2021-01-07 22:22:05 +03:00 |
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AMDGPUInstrInfo.h
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[NFC][AMDGPU] Reduce include files dependency.
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2021-01-07 22:22:05 +03:00 |
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AMDGPUInstrInfo.td
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AMDGPU: Move zeroed FP high bits optimization to patterns
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2021-06-22 12:47:56 -04:00 |
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AMDGPUInstructionSelector.cpp
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[AMDGPU][GlobalISel] Legalize and select G_SBFX and G_UBFX
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2021-06-28 09:06:44 -04:00 |
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AMDGPUInstructionSelector.h
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[AMDGPU][GlobalISel] Legalize and select G_SBFX and G_UBFX
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2021-06-28 09:06:44 -04:00 |
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AMDGPUInstructions.td
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[AMDGPU] Simplify tablegen files. NFC.
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2021-07-07 09:19:23 +01:00 |
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AMDGPULateCodeGenPrepare.cpp
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AMDGPU: Fix assert on constant load from addrspacecasted pointer
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2021-05-11 20:12:20 -04:00 |
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AMDGPULegalizerInfo.cpp
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GlobalISel: Handle lowering non-power-of-2 extloads
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2021-07-14 11:54:11 -04:00 |
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AMDGPULegalizerInfo.h
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[AMDGPU] Remove dead declaration (NFC).
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2021-05-25 16:04:04 +05:30 |
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AMDGPULibCalls.cpp
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[llvm] Rename StringRef _lower() method calls to _insensitive()
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2021-06-25 00:22:01 +03:00 |
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AMDGPULibFunc.cpp
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[amdgpu] Add `-enable-ocl-mangling-mismatch-workaround`.
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2021-06-08 15:42:27 -04:00 |
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AMDGPULibFunc.h
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…
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AMDGPULowerIntrinsics.cpp
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[NFC][AMDGPU] Split AMDGPUSubtarget.h to R600 and GCN subtargets
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2021-01-20 22:22:45 +03:00 |
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AMDGPULowerKernelArguments.cpp
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[CodeGen] Add missing includes (NFC)
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2021-06-06 15:48:27 +02:00 |
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AMDGPULowerKernelAttributes.cpp
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[AMDGPU] Fix pass name of AMDGPULowerKernelAttributes. NFC.
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2021-07-06 15:03:31 -07:00 |
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AMDGPULowerModuleLDSPass.cpp
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[AMDGPU] Check for pointer operand while refining LDS align
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2021-06-23 12:27:55 -07:00 |
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AMDGPUMCInstLower.cpp
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[AMDGPU] Remove SI_MASK_BRANCH
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2021-03-09 09:13:23 +08:00 |
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AMDGPUMIRFormatter.cpp
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[AMDGPU] Implement mir parseCustomPseudoSourceValue
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2021-01-22 11:24:08 +01:00 |
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AMDGPUMIRFormatter.h
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[AMDGPU] Implement mir parseCustomPseudoSourceValue
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2021-01-22 11:24:08 +01:00 |
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AMDGPUMachineCFGStructurizer.cpp
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[AMDGPU] Fix build breakage
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2021-02-14 09:02:55 -08:00 |
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AMDGPUMachineFunction.cpp
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[AMDGPU] Fix module LDS selection
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2021-05-20 15:59:01 -07:00 |
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AMDGPUMachineFunction.h
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[amdgpu] Implement lower function LDS pass
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2021-03-15 15:24:01 +00:00 |
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AMDGPUMachineModuleInfo.cpp
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[NFC][AMDGPU] Reduce include files dependency.
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2021-01-07 22:22:05 +03:00 |
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AMDGPUMachineModuleInfo.h
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[NFC][AMDGPU] Reduce include files dependency.
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2021-01-07 22:22:05 +03:00 |
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AMDGPUMacroFusion.cpp
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[NFC][AMDGPU] Split AMDGPUSubtarget.h to R600 and GCN subtargets
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2021-01-20 22:22:45 +03:00 |
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AMDGPUMacroFusion.h
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[llvm] Add missing header guards (NFC)
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2021-01-30 09:53:42 -08:00 |
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AMDGPUOpenCLEnqueuedBlockLowering.cpp
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[NFC][AMDGPU] Reduce include files dependency.
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2021-01-07 22:22:05 +03:00 |
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AMDGPUPTNote.h
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AMDGPU: Add target id and code object v4 support
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2021-03-24 11:54:05 -04:00 |
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AMDGPUPerfHintAnalysis.cpp
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[CodeGen] Add missing includes (NFC)
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2021-06-06 15:48:27 +02:00 |
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AMDGPUPerfHintAnalysis.h
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[NFC][AMDGPU] Reduce include files dependency.
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2021-01-07 22:22:05 +03:00 |
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AMDGPUPostLegalizerCombiner.cpp
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AMDGPU/GlobalISel: Remove redundant G_FCANONICALIZE
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2021-04-27 12:26:37 +02:00 |
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AMDGPUPreLegalizerCombiner.cpp
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[GISel] Support llvm.memcpy.inline
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2021-06-30 12:39:05 -07:00 |
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AMDGPUPrintfRuntimeBinding.cpp
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[AMDGPU] Simplify GEP construction (NFC)
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2021-07-08 21:21:43 +02:00 |
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AMDGPUPromoteAlloca.cpp
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[OpaquePtr] Create API to make a copy of a PointerType with some address space
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2021-06-01 16:52:32 -07:00 |
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AMDGPUPropagateAttributes.cpp
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Revert "[AMDGPU] [IndirectCalls] Don't propagate attributes to address taken functions and their callees"
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2021-06-24 02:33:50 +01:00 |
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AMDGPURegBankCombiner.cpp
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AMDGPU/GlobalISel: Add integer med3 combines
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2021-04-27 11:52:23 +02:00 |
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AMDGPURegisterBankInfo.cpp
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[AMDGPU][GlobalISel] Legalize and select G_SBFX and G_UBFX
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2021-06-28 09:06:44 -04:00 |
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AMDGPURegisterBankInfo.h
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[AMDGPU][GlobalISel] Legalize and select G_SBFX and G_UBFX
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2021-06-28 09:06:44 -04:00 |
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AMDGPURegisterBanks.td
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[AMDGPU] Add 224-bit vector types and link 192-bit types to MVTs
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2021-06-24 12:41:22 +09:00 |
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AMDGPUReplaceLDSUseWithPointer.cpp
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[AMDGPU] Replace non-kernel function uses of LDS globals by pointers.
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2021-06-21 11:51:49 +05:30 |
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AMDGPURewriteOutArguments.cpp
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[NFC][AMDGPU] Reduce include files dependency.
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2021-01-07 22:22:05 +03:00 |
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AMDGPUSearchableTables.td
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[AMDGPU] gfx90a support
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2021-02-17 16:01:32 -08:00 |
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AMDGPUSubtarget.cpp
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[AMDGPU] Stop mulhi from doing 24 bit mul for uniform values
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2021-07-05 10:33:23 +01:00 |
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AMDGPUSubtarget.h
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[AMDGPU] Stop mulhi from doing 24 bit mul for uniform values
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2021-07-05 10:33:23 +01:00 |
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AMDGPUTargetMachine.cpp
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[AMDGPU] Refine -O0 and -O1 passes.
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2021-07-15 09:51:54 -07:00 |
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AMDGPUTargetMachine.h
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[NewPM] Hide pass manager debug logging behind -debug-pass-manager-verbose
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2021-05-07 21:51:47 -07:00 |
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AMDGPUTargetObjectFile.cpp
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[NFC][AMDGPU] Reduce include files dependency.
|
2021-01-07 22:22:05 +03:00 |
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AMDGPUTargetObjectFile.h
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…
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AMDGPUTargetTransformInfo.cpp
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[TTI] Remove IsPairwiseForm from getArithmeticReductionCost
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2021-07-09 11:51:16 +01:00 |
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AMDGPUTargetTransformInfo.h
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[TTI] Remove IsPairwiseForm from getArithmeticReductionCost
|
2021-07-09 11:51:16 +01:00 |
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AMDGPUUnifyDivergentExitNodes.cpp
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[AMDGPU] Don't handle export done when unify exit nodes
|
2021-07-14 14:54:37 +08:00 |
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AMDGPUUnifyMetadata.cpp
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[NFC][AMDGPU] Reduce include files dependency.
|
2021-01-07 22:22:05 +03:00 |
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AMDILCFGStructurizer.cpp
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[NewPM] Cleanup IR printing instrumentation
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2021-04-15 09:50:55 -07:00 |
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AMDKernelCodeT.h
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[NFC][AMDGPU] Reduce include files dependency.
|
2021-01-07 22:22:05 +03:00 |
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BUFInstructions.td
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[AMDGPU] Simplify tablegen files. NFC.
|
2021-07-07 09:19:23 +01:00 |
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CMakeLists.txt
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[AMDGPU] Add S_MOV_B64_IMM_PSEUDO for wide constants
|
2021-06-30 11:45:38 -07:00 |
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CaymanInstructions.td
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…
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DSInstructions.td
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[AMDGPU] Set IsAtomicRet and IsAtomicNoRet on Real instructions
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2021-06-16 12:23:29 +01:00 |
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EXPInstructions.td
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[AMDGPU] Separate out real exp instructions by subtarget. NFC.
|
2020-11-11 17:13:40 +00:00 |
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EvergreenInstructions.td
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[AMDGPU] Inline FSHRPattern into its only use. NFC.
|
2021-03-26 09:32:02 +00:00 |
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FLATInstructions.td
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[AMDGPU] Set IsAtomicRet and IsAtomicNoRet on Real instructions
|
2021-06-16 12:23:29 +01:00 |
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GCNDPPCombine.cpp
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[AMDGPU] GCNDPPCombine: don't shrink V_ADD_CO_U32 if carry out is used
|
2021-04-20 09:17:52 +01:00 |
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GCNHazardRecognizer.cpp
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[AMDGPU] Limit runs of fixLdsBranchVmemWARHazard
|
2021-06-14 22:30:23 +02:00 |
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GCNHazardRecognizer.h
|
[AMDGPU] Limit runs of fixLdsBranchVmemWARHazard
|
2021-06-14 22:30:23 +02:00 |
|
GCNILPSched.cpp
|
[NFC][AMDGPU] Reduce include files dependency.
|
2021-01-07 22:22:05 +03:00 |
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GCNIterativeScheduler.cpp
|
[NFC][AMDGPU] Split AMDGPUSubtarget.h to R600 and GCN subtargets
|
2021-01-20 22:22:45 +03:00 |
|
GCNIterativeScheduler.h
|
[NFC][AMDGPU] Reduce include files dependency.
|
2021-01-07 22:22:05 +03:00 |
|
GCNMinRegStrategy.cpp
|
[NFC][AMDGPU] Reduce include files dependency.
|
2021-01-07 22:22:05 +03:00 |
|
GCNNSAReassign.cpp
|
[AMDGPU] Do not reassign spilled registers
|
2021-01-27 16:29:05 -08:00 |
|
GCNPreRAOptimizations.cpp
|
[AMDGPU] Add S_MOV_B64_IMM_PSEUDO for wide constants
|
2021-06-30 11:45:38 -07:00 |
|
GCNProcessors.td
|
[AMDGPU] Add gfx1035 target
|
2021-06-24 14:32:41 -04:00 |
|
GCNRegPressure.cpp
|
[AMDGPU] gfx90a support
|
2021-02-17 16:01:32 -08:00 |
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GCNRegPressure.h
|
[AMDGPU] gfx90a support
|
2021-02-17 16:01:32 -08:00 |
|
GCNSchedStrategy.cpp
|
[AMDGPU] Avoid second rescheduling for some regions
|
2021-02-26 12:29:37 -08:00 |
|
GCNSchedStrategy.h
|
[AMDGPU] Avoid second rescheduling for some regions
|
2021-02-26 12:29:37 -08:00 |
|
GCNSubtarget.h
|
AMDGPU: Try to eliminate clearing of high bits of 16-bit instructions
|
2021-06-22 13:42:49 -04:00 |
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InstCombineTables.td
|
…
|
|
|
MIMGInstructions.td
|
Reland "[AMDGPU] Add gfx1013 target"
|
2021-06-08 21:15:35 -04:00 |
|
R600.td
|
…
|
|
|
R600AsmPrinter.cpp
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[NFC][AMDGPU] Split AMDGPUSubtarget.h to R600 and GCN subtargets
|
2021-01-20 22:22:45 +03:00 |
|
R600AsmPrinter.h
|
…
|
|
|
R600ClauseMergePass.cpp
|
[NFC][AMDGPU] Split AMDGPUSubtarget.h to R600 and GCN subtargets
|
2021-01-20 22:22:45 +03:00 |
|
R600ControlFlowFinalizer.cpp
|
[NFC][AMDGPU] Split AMDGPUSubtarget.h to R600 and GCN subtargets
|
2021-01-20 22:22:45 +03:00 |
|
R600Defines.h
|
[NFC][AMDGPU] Reduce include files dependency.
|
2021-01-07 22:22:05 +03:00 |
|
R600EmitClauseMarkers.cpp
|
[NFC][AMDGPU] Split AMDGPUSubtarget.h to R600 and GCN subtargets
|
2021-01-20 22:22:45 +03:00 |
|
R600ExpandSpecialInstrs.cpp
|
[NFC][AMDGPU] Split AMDGPUSubtarget.h to R600 and GCN subtargets
|
2021-01-20 22:22:45 +03:00 |
|
R600FrameLowering.cpp
|
[NFC][AMDGPU] Split AMDGPUSubtarget.h to R600 and GCN subtargets
|
2021-01-20 22:22:45 +03:00 |
|
R600FrameLowering.h
|
[NFC][AMDGPU] Reduce include files dependency.
|
2021-01-07 22:22:05 +03:00 |
|
R600ISelLowering.cpp
|
[DAG] Add a generic expansion for SHIFT_PARTS opcodes using funnel shifts
|
2021-05-07 13:12:30 +01:00 |
|
R600ISelLowering.h
|
[llvm][sve] Lowering for VLS truncating stores
|
2021-07-12 11:14:17 +01:00 |
|
R600InstrFormats.td
|
…
|
|
|
R600InstrInfo.cpp
|
[NFC][AMDGPU] Split AMDGPUSubtarget.h to R600 and GCN subtargets
|
2021-01-20 22:22:45 +03:00 |
|
R600InstrInfo.h
|
Add "SkipDead" parameter to TargetInstrInfo::DefinesPredicate
|
2020-10-21 11:52:47 +01:00 |
|
R600Instructions.td
|
…
|
|
|
R600MachineFunctionInfo.cpp
|
…
|
|
|
R600MachineFunctionInfo.h
|
…
|
|
|
R600MachineScheduler.cpp
|
[NFC][AMDGPU] Split AMDGPUSubtarget.h to R600 and GCN subtargets
|
2021-01-20 22:22:45 +03:00 |
|
R600MachineScheduler.h
|
[AMDGPU] Remove uses of Register::isPhysicalRegister/isVirtualRegister
|
2020-08-20 17:59:11 +01:00 |
|
R600OpenCLImageTypeLoweringPass.cpp
|
TransformUtils: Fix metadata handling in CloneModule (and improve CloneFunctionInto)
|
2021-02-15 11:56:00 -08:00 |
|
R600OptimizeVectorRegisters.cpp
|
[NFC][AMDGPU] Split AMDGPUSubtarget.h to R600 and GCN subtargets
|
2021-01-20 22:22:45 +03:00 |
|
R600Packetizer.cpp
|
[NFC][AMDGPU] Split AMDGPUSubtarget.h to R600 and GCN subtargets
|
2021-01-20 22:22:45 +03:00 |
|
R600Processors.td
|
…
|
|
|
R600RegisterInfo.cpp
|
[NFC][AMDGPU] Split AMDGPUSubtarget.h to R600 and GCN subtargets
|
2021-01-20 22:22:45 +03:00 |
|
R600RegisterInfo.h
|
[AMDGPU] Remove uses of Register::isPhysicalRegister/isVirtualRegister
|
2020-08-20 17:59:11 +01:00 |
|
R600RegisterInfo.td
|
…
|
|
|
R600Schedule.td
|
…
|
|
|
R600Subtarget.h
|
[NFC][AMDGPU] Split AMDGPUSubtarget.h to R600 and GCN subtargets
|
2021-01-20 22:22:45 +03:00 |
|
R700Instructions.td
|
…
|
|
|
SIAnnotateControlFlow.cpp
|
[AMDGPU] Set LoopInfo as preserved by SIAnnotateControlFlow
|
2021-07-08 09:34:43 -07:00 |
|
SIDefines.h
|
[AMDGPU] IsFlatScratch/Global -> FlatScratch/Global
|
2021-04-09 11:20:31 +02:00 |
|
SIFixSGPRCopies.cpp
|
[AMDGPU] Introduce Strict WQM mode
|
2021-03-03 14:19:16 +01:00 |
|
SIFixVGPRCopies.cpp
|
[NFC][AMDGPU] Split AMDGPUSubtarget.h to R600 and GCN subtargets
|
2021-01-20 22:22:45 +03:00 |
|
SIFoldOperands.cpp
|
AMDGPU: Try to eliminate clearing of high bits of 16-bit instructions
|
2021-06-22 13:42:49 -04:00 |
|
SIFormMemoryClauses.cpp
|
[AMDGPU][NFC] Fix typos in SIFormMemoryClauses description
|
2021-05-06 07:47:39 -07:00 |
|
SIFrameLowering.cpp
|
[AMDGPU] Init scratch only if necessary
|
2021-07-14 10:45:22 +02:00 |
|
SIFrameLowering.h
|
[NFC][AMDGPU] Reduce include files dependency.
|
2021-01-07 22:22:05 +03:00 |
|
SIISelLowering.cpp
|
[AMDGPU] Add 224-bit vector types and link 192-bit types to MVTs
|
2021-06-24 12:41:22 +09:00 |
|
SIISelLowering.h
|
[TTI] NFC: Change getTypeLegalizationCost to return InstructionCost.
|
2021-04-30 22:51:51 +03:00 |
|
SIInsertHardClauses.cpp
|
[AMDGPU] Do not clause NSA instructions
|
2021-05-14 12:54:56 +09:00 |
|
SIInsertWaitcnts.cpp
|
[AMDGPU] Remove assert
|
2021-05-12 14:52:37 +02:00 |
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SIInstrFormats.td
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[AMDGPU] IsFlatScratch/Global -> FlatScratch/Global
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2021-04-09 11:20:31 +02:00 |
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SIInstrInfo.cpp
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[AMDGPU] Use isMetaInstruction for instruction size
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2021-07-15 12:23:11 +02:00 |
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SIInstrInfo.h
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[AMDGPU] Add TII::isIgnorableUse() to allow VOP rematerialization
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2021-07-14 13:03:58 -07:00 |
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SIInstrInfo.td
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AMDGPU: Move zeroed FP high bits optimization to patterns
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2021-06-22 12:47:56 -04:00 |
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SIInstructions.td
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[AMDGPU] Mark waterfall loops as SI_WATERFALL_LOOP
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2021-07-13 12:15:08 +02:00 |
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SILateBranchLowering.cpp
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[AMDGPU] Add MDT update missing from D98915
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2021-03-20 13:38:58 +09:00 |
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SILoadStoreOptimizer.cpp
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AMDGPU: Fix SILoadStoreOptimizer for gfx90a
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2021-05-11 21:26:43 -04:00 |
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SILowerControlFlow.cpp
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[AMDGPU] Mark waterfall loops as SI_WATERFALL_LOOP
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2021-07-13 12:15:08 +02:00 |
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SILowerI1Copies.cpp
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[Target] Use llvm::append_range (NFC)
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2021-01-24 12:18:56 -08:00 |
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SILowerSGPRSpills.cpp
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RegAlloc: Allow targets to split register allocation
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2021-07-13 18:49:29 -04:00 |
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SIMachineFunctionInfo.cpp
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[AMDGPU] Init scratch only if necessary
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2021-07-14 10:45:22 +02:00 |
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SIMachineFunctionInfo.h
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[AMDGPU] Serialize MFInfo::ScavengeFI
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2021-05-07 11:15:25 +02:00 |
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SIMachineScheduler.cpp
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[NFC][AMDGPU] Reduce include files dependency.
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2021-01-07 22:22:05 +03:00 |
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SIMachineScheduler.h
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[NFC][AMDGPU] Reduce include files dependency.
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2021-01-07 22:22:05 +03:00 |
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SIMemoryLegalizer.cpp
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[AMDGPU] Update gfx90a memory model support
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2021-06-30 04:05:22 +00:00 |
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SIModeRegister.cpp
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[NFC][AMDGPU] Split AMDGPUSubtarget.h to R600 and GCN subtargets
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2021-01-20 22:22:45 +03:00 |
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SIOptimizeExecMasking.cpp
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[AMDGPU] Move kill lowering to WQM pass and add live mask tracking
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2021-02-11 20:31:29 +09:00 |
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SIOptimizeExecMaskingPreRA.cpp
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[AMDGPU] SIOptimizeExecMaskingPreRA should check constant bus constraint when folds EXEC copy
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2021-03-24 14:14:13 +03:00 |
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SIOptimizeVGPRLiveRange.cpp
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[AMDGPU] Optimize VGPR LiveRange in waterfall loops
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2021-07-13 12:15:08 +02:00 |
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SIPeepholeSDWA.cpp
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[NFC][AMDGPU] Split AMDGPUSubtarget.h to R600 and GCN subtargets
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2021-01-20 22:22:45 +03:00 |
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SIPostRABundler.cpp
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AMDGPU: Use kill instruction to hint soft clause live ranges
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2021-02-26 18:26:40 -05:00 |
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SIPreAllocateWWMRegs.cpp
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[AMDGPU] Save WWM registers in functions
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2021-04-23 18:09:24 +02:00 |
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SIPreEmitPeephole.cpp
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[AMDGPU] Remove set_gpr_idx instructions in conditional blocks
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2021-04-30 22:15:45 +01:00 |
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SIProgramInfo.cpp
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[AMDGPU] Set rsrc1 flags for graphics shaders
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2020-11-04 12:25:41 +01:00 |
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SIProgramInfo.h
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[AMDGPU] gfx90a support
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2021-02-17 16:01:32 -08:00 |
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SIRegisterInfo.cpp
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RegAlloc: Allow targets to split register allocation
|
2021-07-13 18:49:29 -04:00 |
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SIRegisterInfo.h
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RegAlloc: Allow targets to split register allocation
|
2021-07-13 18:49:29 -04:00 |
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SIRegisterInfo.td
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[AMDGPU] Add 224-bit vector types and link 192-bit types to MVTs
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2021-06-24 12:41:22 +09:00 |
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SISchedule.td
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Revert "[MCA] [AMDGPU] Adding an implementation to AMDGPUCustomBehaviour for handling s_waitcnt instructions."
|
2021-07-07 20:48:42 -07:00 |
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SIShrinkInstructions.cpp
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[AMDGPU] Add v5f32/VReg_160 support for MIMG instructions
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2021-06-08 11:11:40 +09:00 |
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SIWholeQuadMode.cpp
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[AMDGPU] Fix WQM failure with single block inactive demote
|
2021-05-06 21:02:26 +09:00 |
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SMInstructions.td
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[AMDGPU] Set IsAtomicRet and IsAtomicNoRet on Real instructions
|
2021-06-16 12:23:29 +01:00 |
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SOPInstructions.td
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[AMDGPU] Mark more SOP instructions as rematerializable
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2021-07-08 16:00:45 -07:00 |
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VIInstrFormats.td
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…
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|
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VOP1Instructions.td
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[AMDGPU] Make some VOP1 instructions rematerializable
|
2021-07-12 23:43:45 -07:00 |
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VOP2Instructions.td
|
[AMDGPU] Use opName instead of PseudoName in VOP2 multiclasses. NFC.
|
2021-06-28 16:46:35 +01:00 |
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VOP3Instructions.td
|
[AMDGPU] Tweak VOP3_INTERP16 profile
|
2021-05-17 15:28:00 +01:00 |
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VOP3PInstructions.td
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[AMDGPU] Set VOP3P flag on Real instructions
|
2021-06-16 15:00:45 +01:00 |
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VOPCInstructions.td
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[AMDGPU] Set SALU, VALU and other instruction type flags on Real instructions
|
2021-06-16 13:36:02 +01:00 |
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VOPInstructions.td
|
[AMDGPU] Set SALU, VALU and other instruction type flags on Real instructions
|
2021-06-16 13:36:02 +01:00 |
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