..
32-bit-local-address-space.ll
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README
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add-debug.ll
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add.ll
AMDGPU: Add sdst operand to VOP2b instructions
2015-08-29 07:16:50 +00:00
add_i64.ll
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address-space.ll
PeepholeOptimizer: Remove redundant copies
2015-09-25 20:22:12 +00:00
addrspacecast.ll
AMDGPU: Error on addrspacecasts that aren't actually implemented
2015-12-01 23:04:05 +00:00
and.ll
AMDGPU: Add some more tests for literal operands
2015-09-25 18:21:47 +00:00
annotate-kernel-features.ll
AMDGPU: Add pass to detect used kernel features
2015-11-06 18:01:57 +00:00
anyext.ll
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array-ptr-calc-i32.ll
AMDGPU: Add sdst operand to VOP2b instructions
2015-08-29 07:16:50 +00:00
array-ptr-calc-i64.ll
AMDGPU: Avoid using 64-bit shift for i64 (shl x, 32)
2015-07-14 18:20:33 +00:00
atomic_cmp_swap_local.ll
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atomic_load_add.ll
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atomic_load_sub.ll
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basic-branch.ll
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basic-loop.ll
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bfe_uint.ll
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bfi_int.ll
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big_alu.ll
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bitcast.ll
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bitreverse.ll
AMDGPU: Use generic bitreverse intrinsic
2015-12-14 17:25:38 +00:00
bswap.ll
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build_vector.ll
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call.ll
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call_fs.ll
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calling-conventions.ll
AMDGPU/SI: Remove calling convention assertion from LowerFormalArguments()
2015-10-06 21:16:34 +00:00
cayman-loop-bug.ll
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cf-stack-bug.ll
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cf_end.ll
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cgp-addressing-modes-flat.ll
AMDGPU: Implement isNoopAddrSpaceCast
2015-12-01 23:04:00 +00:00
cgp-addressing-modes.ll
AMDGPU/SI: Fold operands through REG_SEQUENCE instructions
2015-09-09 15:43:26 +00:00
coalescer_remat.ll
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codegen-prepare-addrmode-sext.ll
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combine_vloads.ll
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commute-compares.ll
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commute-shifts.ll
AMDGPU: really don't commute REV opcodes if the target variant doesn't exist
2015-06-26 20:29:10 +00:00
commute_modifiers.ll
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complex-folding.ll
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concat_vectors.ll
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copy-illegal-type.ll
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copy-to-reg.ll
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ctlz_zero_undef.ll
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ctpop.ll
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ctpop64.ll
AMDGPU: Reduce number of copies emitted
2015-09-24 07:16:37 +00:00
cttz_zero_undef.ll
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cvt_f32_ubyte.ll
AMDGPU: Split x8 and x16 vector loads instead of scalarize
2015-11-24 12:05:03 +00:00
cvt_flr_i32_f32.ll
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cvt_rpi_i32_f32.ll
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dagcombiner-bug-illegal-vec4-int-to-fp.ll
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debug.ll
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default-fp-mode.ll
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disconnected-predset-break-bug.ll
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dot4-folding.ll
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drop-mem-operand-move-smrd.ll
AMDGPU: Fix dropping mem operands when moving to VALU
2015-08-29 06:48:46 +00:00
ds-negative-offset-addressing-mode-loop.ll
AMDGPU: Add sdst operand to VOP2b instructions
2015-08-29 07:16:50 +00:00
ds-sub-offset.ll
AMDGPU: Handle sub of constant for DS offset folding
2015-09-08 19:34:22 +00:00
ds_read2.ll
DAGCombiner: Combine extract_vector_elt from build_vector
2015-10-12 23:59:50 +00:00
ds_read2_offset_order.ll
AMDGPU/SI: Fix read2 merging into a super register.
2015-07-14 17:57:36 +00:00
ds_read2_superreg.ll
AMDGPU: Make v2i64/v2f64 legal types.
2015-11-25 19:58:34 +00:00
ds_read2st64.ll
AMDGPU: Add sdst operand to VOP2b instructions
2015-08-29 07:16:50 +00:00
ds_write2.ll
AMDGPU: Make v2i64/v2f64 legal types.
2015-11-25 19:58:34 +00:00
ds_write2st64.ll
AMDGPU/SI: Fix read2 merging into a super register.
2015-07-14 17:57:36 +00:00
dynamic_stackalloc.ll
AMDGPU: Produce error on dynamic_stackalloc
2015-08-26 18:37:13 +00:00
elf.ll
AMDGPU/SI: Set ELF OS/ABI to ELFOSABI_AMDGPU_HSA
2015-06-26 21:15:11 +00:00
elf.r600.ll
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empty-function.ll
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endcf-loop-header.ll
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extload-private.ll
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extload.ll
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extract-vector-elt-i64.ll
AMDGPU: Make v2i64/v2f64 legal types.
2015-11-25 19:58:34 +00:00
extract_vector_elt_i16.ll
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fabs.f64.ll
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fabs.ll
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fadd.ll
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fadd64.ll
AMDGPU: Make v2i64/v2f64 legal types.
2015-11-25 19:58:34 +00:00
fceil.ll
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fceil64.ll
DAGCombiner: Combine extract_vector_elt from build_vector
2015-10-12 23:59:50 +00:00
fcmp-cnd.ll
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fcmp-cnde-int-args.ll
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fcmp.ll
Fix CHECK directives that weren't checking.
2015-08-31 21:10:35 +00:00
fcmp64.ll
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fconst64.ll
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fcopysign.f32.ll
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fcopysign.f64.ll
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fdiv.f64.ll
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fdiv.ll
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fetch-limits.r600.ll
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fetch-limits.r700+.ll
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ffloor.f64.ll
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ffloor.ll
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flat-address-space.ll
AMDGPU: Error on addrspacecasts that aren't actually implemented
2015-12-01 23:04:05 +00:00
floor.ll
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fma-combine.ll
[DAGCombiner] Improve FMA support for interpolation patterns
2015-09-21 20:32:48 +00:00
fma.f64.ll
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fma.ll
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fmad.ll
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fmax.ll
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fmax3.f64.ll
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fmax3.ll
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fmax_legacy.f64.ll
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fmax_legacy.ll
SelectionDAG: Match min/max if the scalar operation is legal
2015-12-11 23:16:47 +00:00
fmaxnum.f64.ll
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fmaxnum.ll
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fmin.ll
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fmin3.ll
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fmin_legacy.f64.ll
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fmin_legacy.ll
SelectionDAG: Match min/max if the scalar operation is legal
2015-12-11 23:16:47 +00:00
fminnum.f64.ll
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fminnum.ll
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fmul-2-combine-multi-use.ll
Only do fmul (fadd x, x), c combine if the fadd only has one use
2015-07-17 01:14:35 +00:00
fmul.ll
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fmul64.ll
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fmuladd.ll
AMDGPU/SI: Select mad patterns to v_mac_f32
2015-07-13 15:47:57 +00:00
fnearbyint.ll
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fneg-fabs.f64.ll
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fneg-fabs.ll
AMDGPU/SI: use S_OR for fneg (fabs f32)
2015-10-29 15:29:05 +00:00
fneg.f64.ll
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fneg.ll
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fp-classify.ll
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fp16_to_fp.ll
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fp32_to_fp16.ll
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fp_to_sint.f64.ll
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fp_to_sint.ll
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fp_to_uint.f64.ll
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fp_to_uint.ll
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fpext.ll
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fptrunc.ll
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frem.ll
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fsqrt.ll
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fsub.ll
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fsub64.ll
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ftrunc.f64.ll
Revert "Remove unnecessary call to getAllocatableRegClass"
2015-11-12 21:43:25 +00:00
ftrunc.ll
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gep-address-space.ll
DAGCombiner: Combine extract_vector_elt from build_vector
2015-10-12 23:59:50 +00:00
global-constant.ll
AMDGPU/SI: Emit constant arrays in the .text section
2015-12-10 02:13:01 +00:00
global-directive.ll
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global-extload-i1.ll
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global-extload-i8.ll
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global-extload-i16.ll
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global-extload-i32.ll
AMDGPU: Make v2i64/v2f64 legal types.
2015-11-25 19:58:34 +00:00
global-zero-initializer.ll
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global_atomics.ll
AMDGPU: Fix printing trailing whitespace for mubuf atomics
2015-09-24 07:51:17 +00:00
gv-const-addrspace-fail.ll
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gv-const-addrspace.ll
AMDGPU: don't match vgpr loads for constant loads
2015-07-27 18:16:08 +00:00
half.ll
AMDGPU: Make v2i64/v2f64 legal types.
2015-11-25 19:58:34 +00:00
hsa-globals.ll
AMDGPU/SI: Emit constant arrays in the .hsrodata_readonly_agent section
2015-12-03 03:34:32 +00:00
hsa-group-segment.ll
AMDGPU/SI: Don't emit group segment global variables
2015-12-02 17:00:42 +00:00
hsa.ll
AMDGPU: Rework how private buffer passed for HSA
2015-11-30 21:16:03 +00:00
i1-copy-implicit-def.ll
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i1-copy-phi.ll
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i8-to-double-to-float.ll
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icmp-select-sete-reverse-args.ll
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icmp64.ll
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image-attributes.ll
ScheduleDAGInstrs: Rework schedule graph builder.
2015-12-04 01:51:19 +00:00
image-resource-id.ll
AMDGPU: Add pass to lower OpenCL image and sampler arguments.
2015-08-07 23:19:30 +00:00
imm.ll
AMDGPU: Distribute SGPR->VGPR copies of REG_SEQUENCE
2015-11-02 23:15:42 +00:00
indirect-addressing-si.ll
AMDGPU: Use explicit register size indirect pseudos
2015-10-07 00:42:51 +00:00
indirect-private-64.ll
AMDGPU: Split LDS vector loads
2015-11-24 12:18:54 +00:00
infinite-loop-evergreen.ll
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infinite-loop.ll
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inline-asm.ll
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inline-calls.ll
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inline-constraints.ll
AMDGPU/SI: Add support for sgpr and vgpr inline assembly constraints
2015-12-10 02:12:53 +00:00
input-mods.ll
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insert_subreg.ll
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insert_vector_elt.ll
AMDGPU: Make v2i64/v2f64 legal types.
2015-11-25 19:58:34 +00:00
invariant-load-no-alias-store.ll
DAGCombiner: Assume invariant load cannot alias a store
2015-07-10 22:17:40 +00:00
jump-address.ll
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kcache-fold.ll
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kernel-args.ll
AMDGPU: Remove SIPrepareScratchRegs
2015-11-30 21:15:53 +00:00
large-alloca-compute.ll
AMDGPU: Rework how private buffer passed for HSA
2015-11-30 21:16:03 +00:00
large-alloca-graphics.ll
AMDGPU: Rework how private buffer passed for HSA
2015-11-30 21:16:03 +00:00
large-constant-initializer.ll
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lds-initializer.ll
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lds-oqap-crash.ll
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lds-output-queue.ll
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lds-size.ll
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lds-zero-initializer.ll
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legalizedag-bug-expand-setcc.ll
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lit.local.cfg
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literals.ll
ScheduleDAGInstrs: Rework schedule graph builder.
2015-12-04 01:51:19 +00:00
llvm.AMDGPU.abs.ll
AMDGPU/SI: select S_ABS_I32 when possible (v2)
2015-11-25 21:22:45 +00:00
llvm.AMDGPU.barrier.global.ll
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llvm.AMDGPU.barrier.local.ll
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llvm.AMDGPU.bfe.i32.ll
AMDGPU: Add sdst operand to VOP2b instructions
2015-08-29 07:16:50 +00:00
llvm.AMDGPU.bfe.u32.ll
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llvm.AMDGPU.bfi.ll
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llvm.AMDGPU.bfm.ll
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llvm.AMDGPU.clamp.ll
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llvm.AMDGPU.class.ll
AMDGPU: Improve accuracy of instruction rates for VOPC
2015-09-25 16:58:25 +00:00
llvm.AMDGPU.cube.ll
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llvm.AMDGPU.cvt_f32_ubyte.ll
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llvm.AMDGPU.div_fixup.ll
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llvm.AMDGPU.div_fmas.ll
AMDGPU/SI: Fix extra space when printing v_div_fmas_*
2015-06-28 18:16:14 +00:00
llvm.AMDGPU.div_scale.ll
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llvm.AMDGPU.flbit.i32.ll
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llvm.AMDGPU.fract.f64.ll
AMDGPU/SI: Fix the V_FRACT_F64 SI bug workaround
2015-07-27 11:37:42 +00:00
llvm.AMDGPU.fract.ll
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llvm.AMDGPU.imad24.ll
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llvm.AMDGPU.imax.ll
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llvm.AMDGPU.imin.ll
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llvm.AMDGPU.imul24.ll
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llvm.AMDGPU.kill.ll
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llvm.AMDGPU.ldexp.ll
…
llvm.AMDGPU.legacy.rsq.ll
…
llvm.AMDGPU.mul.ll
…
llvm.AMDGPU.rcp.f64.ll
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llvm.AMDGPU.rcp.ll
…
llvm.AMDGPU.read.workdim.ll
ScheduleDAGInstrs: Rework schedule graph builder.
2015-12-04 01:51:19 +00:00
llvm.AMDGPU.rsq.clamped.f64.ll
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llvm.AMDGPU.rsq.clamped.ll
…
llvm.AMDGPU.rsq.ll
…
llvm.AMDGPU.tex.ll
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llvm.AMDGPU.trig_preop.ll
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llvm.AMDGPU.trunc.ll
ScheduleDAGInstrs: Rework schedule graph builder.
2015-12-04 01:51:19 +00:00
llvm.AMDGPU.umad24.ll
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llvm.AMDGPU.umax.ll
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llvm.AMDGPU.umin.ll
…
llvm.AMDGPU.umul24.ll
…
llvm.SI.fs.interp.ll
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llvm.SI.gather4.ll
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llvm.SI.getlod.ll
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llvm.SI.image.ll
…
llvm.SI.image.sample.ll
…
llvm.SI.image.sample.o.ll
…
llvm.SI.imageload.ll
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llvm.SI.load.dword.ll
…
llvm.SI.packf16.ll
AMDGPU/SI: handle undef for llvm.SI.packf16
2015-10-29 15:29:09 +00:00
llvm.SI.resinfo.ll
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llvm.SI.sample-masked.ll
…
llvm.SI.sample.ll
…
llvm.SI.sampled.ll
…
llvm.SI.sendmsg-m0.ll
…
llvm.SI.sendmsg.ll
…
llvm.SI.tbuffer.store.ll
…
llvm.SI.tid.ll
…
llvm.amdgcn.buffer.wbinvl1.ll
AMDGPU: Add cache invalidation instructions.
2015-09-24 19:52:21 +00:00
llvm.amdgcn.buffer.wbinvl1.sc.ll
AMDGPU: Add cache invalidation instructions.
2015-09-24 19:52:21 +00:00
llvm.amdgcn.buffer.wbinvl1.vol.ll
AMDGPU: Add cache invalidation instructions.
2015-09-24 19:52:21 +00:00
llvm.amdgcn.dispatch.ptr.ll
AMDGPU: Rework how private buffer passed for HSA
2015-11-30 21:16:03 +00:00
llvm.amdgcn.interp.ll
AMDGPU/SI: Add llvm.amdgcn.v.interp.p[12] intrinsics
2015-12-15 17:02:49 +00:00
llvm.amdgcn.mbcnt.ll
AMDGPU/SI: Add llvm.amdgcn.mbcnt.* intrinsics
2015-12-15 17:02:52 +00:00
llvm.amdgcn.s.dcache.inv.ll
AMDGPU: Add s_dcache_* instructions
2015-09-24 19:52:27 +00:00
llvm.amdgcn.s.dcache.inv.vol.ll
AMDGPU: Add s_dcache_* instructions
2015-09-24 19:52:27 +00:00
llvm.amdgcn.s.dcache.wb.ll
AMDGPU: Add s_dcache_* instructions
2015-09-24 19:52:27 +00:00
llvm.amdgcn.s.dcache.wb.vol.ll
AMDGPU: Add s_dcache_* instructions
2015-09-24 19:52:27 +00:00
llvm.amdgpu.dp4.ll
…
llvm.amdgpu.kilp.ll
…
llvm.amdgpu.lrp.ll
[DAGCombiner] Improve FMA support for interpolation patterns
2015-09-21 20:32:48 +00:00
llvm.cos.ll
…
llvm.dbg.value.ll
AMDGPU: Rework how private buffer passed for HSA
2015-11-30 21:16:03 +00:00
llvm.exp2.ll
…
llvm.log2.ll
…
llvm.memcpy.ll
AMDGPU: Split LDS vector loads
2015-11-24 12:18:54 +00:00
llvm.pow.ll
…
llvm.r600.read.local.size.ll
ScheduleDAGInstrs: Rework schedule graph builder.
2015-12-04 01:51:19 +00:00
llvm.rint.f64.ll
…
llvm.rint.ll
…
llvm.round.f64.ll
Revert "Remove unnecessary call to getAllocatableRegClass"
2015-11-12 21:43:25 +00:00
llvm.round.ll
AMDGPU/SI: Add support for shrinking v_cndmask_b32_e32 instructions
2015-07-14 14:15:03 +00:00
llvm.sin.ll
…
llvm.sqrt.ll
…
load-i1.ll
…
load-input-fold.ll
…
load.ll
AMDGPU: Split x8 and x16 vector loads instead of scalarize
2015-11-24 12:05:03 +00:00
load.vec.ll
…
load64.ll
…
local-64.ll
…
local-atomics.ll
…
local-atomics64.ll
…
local-memory-two-objects.ll
AMDGPU: Rework how private buffer passed for HSA
2015-11-30 21:16:03 +00:00
local-memory.ll
AMDGPU: Rework how private buffer passed for HSA
2015-11-30 21:16:03 +00:00
loop-address.ll
…
loop-idiom.ll
…
lshl.ll
…
lshr.ll
…
m0-spill.ll
…
mad-combine.ll
AMDGPU/SI: Select mad patterns to v_mac_f32
2015-07-13 15:47:57 +00:00
mad-sub.ll
AMDGPU/SI: Select mad patterns to v_mac_f32
2015-07-13 15:47:57 +00:00
mad_int24.ll
…
mad_uint24.ll
…
madak.ll
AMDGPU/SI: Select mad patterns to v_mac_f32
2015-07-13 15:47:57 +00:00
madmk.ll
AMDGPU/SI: Select mad patterns to v_mac_f32
2015-07-13 15:47:57 +00:00
max-literals.ll
…
max.ll
SelectionDAG: Match min/max if the scalar operation is legal
2015-12-11 23:16:47 +00:00
max3.ll
…
merge-stores.ll
AMDGPU: Add some tests for promotion of v2i64 scalar_to_vector
2015-11-25 20:01:03 +00:00
min.ll
SelectionDAG: Match min/max if the scalar operation is legal
2015-12-11 23:16:47 +00:00
min3.ll
…
missing-store.ll
…
move-addr64-rsrc-dead-subreg-writes.ll
Introduce target hook for optimizing register copies
2015-09-24 08:36:14 +00:00
move-to-valu-atomicrmw.ll
AMDGPU: Fix assert when legalizing atomic operands
2015-11-05 02:46:56 +00:00
mubuf.ll
…
mul.ll
…
mul_int24.ll
…
mul_uint24.ll
AMDGPU: Avoid using 64-bit shift for i64 (shl x, 32)
2015-07-14 18:20:33 +00:00
mulhu.ll
…
no-hsa-graphics-shaders.ll
AMDGPU: Error on graphics shaders with HSA
2015-11-02 23:23:02 +00:00
no-initializer-constant-addrspace.ll
…
no-shrink-extloads.ll
DAGCombiner: Check shouldReduceLoadWidth before combining (and (load), x) -> extload
2015-11-06 21:58:37 +00:00
opencl-image-metadata.ll
AMDGPU/SI: Remove assert from AMDGPUOpenCLImageTypeLowering pass
2015-10-01 21:16:05 +00:00
operand-folding.ll
AMDGPU: Add sdst operand to VOP2b instructions
2015-08-29 07:16:50 +00:00
operand-spacing.ll
…
or.ll
ScheduleDAGInstrs: Rework schedule graph builder.
2015-12-04 01:51:19 +00:00
packetizer.ll
…
parallelandifcollapse.ll
…
parallelorifcollapse.ll
…
partially-dead-super-register-immediate.ll
LiveIntervalAnalysis: Avoid multiple connected liveness components
2015-09-22 22:37:44 +00:00
predicate-dp4.ll
…
predicates.ll
…
private-memory-atomics.ll
…
private-memory-broken.ll
…
private-memory.ll
AMDPGU/SI: Negative offsets aren't allowed in MUBUF's vaddr operand
2015-07-16 19:40:09 +00:00
promote-alloca-bitcast-function.ll
AMDGPU: Fix crash if called function is a bitcast
2015-07-28 18:29:14 +00:00
promote-alloca-stored-pointer-value.ll
AMDGPU: Don't try to use LDS/vector for private if pointer value stored
2015-07-28 18:47:00 +00:00
pv-packing.ll
…
pv.ll
…
r600-encoding.ll
…
r600-export-fix.ll
…
r600-infinite-loop-bug-while-reorganizing-vector.ll
…
r600cfg.ll
…
reciprocal.ll
…
register-count-comments.ll
AMDGPU/SI: Fix printing useless info with amdhsa
2015-08-15 00:12:39 +00:00
reorder-stores.ll
AMDGPU: Make v2i64/v2f64 legal types.
2015-11-25 19:58:34 +00:00
rotl.i64.ll
…
rotl.ll
…
rotr.i64.ll
…
rotr.ll
…
rsq.ll
…
rv7x0_count3.ll
…
s_movk_i32.ll
AMDGPU: Reduce number of copies emitted
2015-09-24 07:16:37 +00:00
saddo.ll
…
salu-to-valu.ll
AMDGPU/SI: Select constant loads with non-uniform addresses to MUBUF instructions
2015-12-15 20:55:55 +00:00
sampler-resource-id.ll
AMDGPU: Add pass to lower OpenCL image and sampler arguments.
2015-08-07 23:19:30 +00:00
scalar_to_vector.ll
…
schedule-fs-loop-nested-if.ll
…
schedule-fs-loop-nested.ll
…
schedule-fs-loop.ll
…
schedule-global-loads.ll
…
schedule-if-2.ll
…
schedule-if.ll
…
schedule-kernel-arg-loads.ll
…
schedule-vs-if-nested-loop-failure.ll
…
schedule-vs-if-nested-loop.ll
…
scratch-buffer.ll
AMDGPU: Add sdst operand to VOP2b instructions
2015-08-29 07:16:50 +00:00
sdiv.ll
…
sdivrem24.ll
…
sdivrem64.ll
…
select-i1.ll
…
select-vectors.ll
AMDGPU/SI: Add support for shrinking v_cndmask_b32_e32 instructions
2015-07-14 14:15:03 +00:00
select.ll
…
select64.ll
AMDGPU/SI: Fold operands through REG_SEQUENCE instructions
2015-09-09 15:43:26 +00:00
selectcc-cnd.ll
…
selectcc-cnde-int.ll
…
selectcc-icmp-select-float.ll
…
selectcc-opt.ll
…
selectcc.ll
…
set-dx10.ll
ScheduleDAGInstrs: Rework schedule graph builder.
2015-12-04 01:51:19 +00:00
setcc-equivalent.ll
…
setcc-opt.ll
DAGCombiner: Check shouldReduceLoadWidth before combining (and (load), x) -> extload
2015-11-06 21:58:37 +00:00
setcc.ll
…
setcc64.ll
…
seto.ll
…
setuo.ll
…
sext-eliminate.ll
…
sext-in-reg.ll
ScheduleDAGInstrs: Rework schedule graph builder.
2015-12-04 01:51:19 +00:00
sgpr-control-flow.ll
…
sgpr-copy-duplicate-operand.ll
…
sgpr-copy.ll
…
shared-op-cycle.ll
…
shl.ll
ScheduleDAGInstrs: Rework schedule graph builder.
2015-12-04 01:51:19 +00:00
shl_add_constant.ll
AMDGPU: Add sdst operand to VOP2b instructions
2015-08-29 07:16:50 +00:00
shl_add_ptr.ll
AMDGPU: Add sdst operand to VOP2b instructions
2015-08-29 07:16:50 +00:00
si-annotate-cf-assertion.ll
…
si-annotate-cf.ll
…
si-instr-info-correct-implicit-operands.ll
AMDGPU: Don't reserve SCRATCH_PTR input register
2015-11-30 15:46:47 +00:00
si-literal-folding.ll
AMDGPU/SI: Add test for folding constants into operands
2015-08-27 17:41:27 +00:00
si-lod-bias.ll
…
si-sgpr-spill.ll
AMDGPU: Remove SIPrepareScratchRegs
2015-11-30 21:15:53 +00:00
si-spill-cf.ll
…
si-triv-disjoint-mem-access.ll
AMDGPU: Fix sched model for VOP2b instructions
2015-09-26 02:25:45 +00:00
si-vector-hang.ll
…
sign_extend.ll
…
simplify-demanded-bits-build-pair.ll
…
sint_to_fp.f64.ll
AMDGPU: Improve accuracy of instruction rates for some FP instructions
2015-08-22 00:50:41 +00:00
sint_to_fp.ll
…
sminmax.ll
SelectionDAG: Match min/max if the scalar operation is legal
2015-12-11 23:16:47 +00:00
smrd.ll
AMDGPU/SI: Add support for 32-bit immediate SMRD offsets on CI
2015-08-06 19:28:38 +00:00
split-scalar-i64-add.ll
AMDGPU: Stop assuming vreg for build_vector
2015-11-02 23:30:48 +00:00
split-vector-memoperand-offsets.ll
AMDGPU: Fix splitting vector loads with existing offsets
2015-12-14 16:59:40 +00:00
sra.ll
ScheduleDAGInstrs: Rework schedule graph builder.
2015-12-04 01:51:19 +00:00
srem.ll
…
srl.ll
ScheduleDAGInstrs: Rework schedule graph builder.
2015-12-04 01:51:19 +00:00
ssubo.ll
…
store-barrier.ll
…
store-v3i32.ll
…
store-v3i64.ll
…
store-vector-ptrs.ll
…
store.ll
AMDGPU: Split LDS vector loads
2015-11-24 12:18:54 +00:00
store.r600.ll
…
store_typed.ll
AMDGPU: Add MEM_RAT STORE_TYPED.
2015-10-01 17:51:34 +00:00
structurize.ll
…
structurize1.ll
…
sub.ll
AMDGPU: Add sdst operand to VOP2b instructions
2015-08-29 07:16:50 +00:00
subreg-coalescer-crash.ll
…
subreg-coalescer-undef-use.ll
Test for specific output in lit test
2015-07-01 22:34:59 +00:00
subreg-eliminate-dead.ll
…
swizzle-export.ll
…
tex-clause-antidep.ll
…
texture-input-merge.ll
…
trunc-cmp-constant.ll
…
trunc-store-f64-to-f16.ll
…
trunc-store-i1.ll
…
trunc-store.ll
AMDGPU: Fix v16i32 to v16i8 truncstore
2015-07-31 04:12:04 +00:00
trunc-vector-store-assertion-failure.ll
…
trunc.ll
AMDGPU/SI: use S_AND for i1 trunc
2015-10-29 15:05:03 +00:00
tti-unroll-prefs.ll
…
uaddo.ll
…
udiv.ll
…
udivrem.ll
AMDGPU: Stop reserving v[254:255]
2015-10-20 03:59:58 +00:00
udivrem24.ll
…
udivrem64.ll
…
uint_to_fp.f64.ll
AMDGPU: Improve accuracy of instruction rates for some FP instructions
2015-08-22 00:50:41 +00:00
uint_to_fp.ll
…
unaligned-load-store.ll
…
unhandled-loop-condition-assertion.ll
…
unroll.ll
…
unsupported-cc.ll
ScheduleDAGInstrs: Rework schedule graph builder.
2015-12-04 01:51:19 +00:00
urecip.ll
…
urem.ll
…
use-sgpr-multiple-times.ll
AMDGPU: Distribute SGPR->VGPR copies of REG_SEQUENCE
2015-11-02 23:15:42 +00:00
usubo.ll
…
v1i64-kernel-arg.ll
…
v_cndmask.ll
…
v_mac.ll
AMDGPU/SI: Select mad patterns to v_mac_f32
2015-07-13 15:47:57 +00:00
valu-i1.ll
AMDGPU: Hack for VS_32 register pressure
2015-11-06 17:54:43 +00:00
vector-alloca.ll
…
vertex-fetch-encoding.ll
…
vgpr-spill-emergency-stack-slot-compute.ll
AMDGPU: Rework how private buffer passed for HSA
2015-11-30 21:16:03 +00:00
vgpr-spill-emergency-stack-slot.ll
AMDGPU: Rework how private buffer passed for HSA
2015-11-30 21:16:03 +00:00
vop-shrink.ll
AMDGPU: Add sdst operand to VOP2b instructions
2015-08-29 07:16:50 +00:00
vselect.ll
AMDGPU/SI: Add support for shrinking v_cndmask_b32_e32 instructions
2015-07-14 14:15:03 +00:00
vselect64.ll
…
vtx-fetch-branch.ll
…
vtx-schedule.ll
…
wait.ll
AMDGPU/SI: Better handle s_wait insertion
2015-08-21 22:47:27 +00:00
work-item-intrinsics.ll
ScheduleDAGInstrs: Rework schedule graph builder.
2015-12-04 01:51:19 +00:00
wrong-transalu-pos-fix.ll
…
xor.ll
ScheduleDAGInstrs: Rework schedule graph builder.
2015-12-04 01:51:19 +00:00
zero_extend.ll
AMDGPU: Distribute SGPR->VGPR copies of REG_SEQUENCE
2015-11-02 23:15:42 +00:00