forked from OSchip/llvm-project
199 lines
6.4 KiB
C++
199 lines
6.4 KiB
C++
//===- R600MCCodeEmitter.cpp - Code Emitter for R600->Cayman GPU families -===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file
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///
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/// The R600 code emitter produces machine code that can be executed
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/// directly on the GPU device.
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//
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//===----------------------------------------------------------------------===//
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#include "MCTargetDesc/AMDGPUFixupKinds.h"
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#include "MCTargetDesc/AMDGPUMCTargetDesc.h"
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#include "R600Defines.h"
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#include "llvm/MC/MCCodeEmitter.h"
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#include "llvm/MC/MCContext.h"
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#include "llvm/MC/MCFixup.h"
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#include "llvm/MC/MCInst.h"
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#include "llvm/MC/MCInstrDesc.h"
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#include "llvm/MC/MCInstrInfo.h"
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#include "llvm/MC/MCRegisterInfo.h"
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#include "llvm/MC/MCSubtargetInfo.h"
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#include "llvm/Support/Endian.h"
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#include "llvm/Support/EndianStream.h"
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#include "llvm/Support/raw_ostream.h"
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#include <cassert>
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#include <cstdint>
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using namespace llvm;
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namespace {
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class R600MCCodeEmitter : public MCCodeEmitter {
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const MCRegisterInfo &MRI;
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const MCInstrInfo &MCII;
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public:
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R600MCCodeEmitter(const MCInstrInfo &mcii, const MCRegisterInfo &mri)
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: MRI(mri), MCII(mcii) {}
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R600MCCodeEmitter(const R600MCCodeEmitter &) = delete;
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R600MCCodeEmitter &operator=(const R600MCCodeEmitter &) = delete;
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/// Encode the instruction and write it to the OS.
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void encodeInstruction(const MCInst &MI, raw_ostream &OS,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const;
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/// \returns the encoding for an MCOperand.
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uint64_t getMachineOpValue(const MCInst &MI, const MCOperand &MO,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const;
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private:
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void Emit(uint32_t value, raw_ostream &OS) const;
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void Emit(uint64_t value, raw_ostream &OS) const;
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unsigned getHWReg(unsigned regNo) const;
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uint64_t getBinaryCodeForInstr(const MCInst &MI,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const;
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uint64_t computeAvailableFeatures(const FeatureBitset &FB) const;
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void verifyInstructionPredicates(const MCInst &MI,
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uint64_t AvailableFeatures) const;
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};
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} // end anonymous namespace
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enum RegElement {
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ELEMENT_X = 0,
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ELEMENT_Y,
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ELEMENT_Z,
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ELEMENT_W
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};
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enum FCInstr {
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FC_IF_PREDICATE = 0,
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FC_ELSE,
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FC_ENDIF,
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FC_BGNLOOP,
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FC_ENDLOOP,
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FC_BREAK_PREDICATE,
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FC_CONTINUE
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};
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MCCodeEmitter *llvm::createR600MCCodeEmitter(const MCInstrInfo &MCII,
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const MCRegisterInfo &MRI,
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MCContext &Ctx) {
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return new R600MCCodeEmitter(MCII, MRI);
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}
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void R600MCCodeEmitter::encodeInstruction(const MCInst &MI, raw_ostream &OS,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const {
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verifyInstructionPredicates(MI,
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computeAvailableFeatures(STI.getFeatureBits()));
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const MCInstrDesc &Desc = MCII.get(MI.getOpcode());
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if (MI.getOpcode() == R600::RETURN ||
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MI.getOpcode() == R600::FETCH_CLAUSE ||
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MI.getOpcode() == R600::ALU_CLAUSE ||
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MI.getOpcode() == R600::BUNDLE ||
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MI.getOpcode() == R600::KILL) {
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return;
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} else if (IS_VTX(Desc)) {
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uint64_t InstWord01 = getBinaryCodeForInstr(MI, Fixups, STI);
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uint32_t InstWord2 = MI.getOperand(2).getImm(); // Offset
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if (!(STI.getFeatureBits()[R600::FeatureCaymanISA])) {
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InstWord2 |= 1 << 19; // Mega-Fetch bit
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}
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Emit(InstWord01, OS);
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Emit(InstWord2, OS);
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Emit((uint32_t) 0, OS);
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} else if (IS_TEX(Desc)) {
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int64_t Sampler = MI.getOperand(14).getImm();
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int64_t SrcSelect[4] = {
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MI.getOperand(2).getImm(),
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MI.getOperand(3).getImm(),
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MI.getOperand(4).getImm(),
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MI.getOperand(5).getImm()
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};
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int64_t Offsets[3] = {
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MI.getOperand(6).getImm() & 0x1F,
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MI.getOperand(7).getImm() & 0x1F,
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MI.getOperand(8).getImm() & 0x1F
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};
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uint64_t Word01 = getBinaryCodeForInstr(MI, Fixups, STI);
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uint32_t Word2 = Sampler << 15 | SrcSelect[ELEMENT_X] << 20 |
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SrcSelect[ELEMENT_Y] << 23 | SrcSelect[ELEMENT_Z] << 26 |
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SrcSelect[ELEMENT_W] << 29 | Offsets[0] << 0 | Offsets[1] << 5 |
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Offsets[2] << 10;
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Emit(Word01, OS);
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Emit(Word2, OS);
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Emit((uint32_t) 0, OS);
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} else {
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uint64_t Inst = getBinaryCodeForInstr(MI, Fixups, STI);
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if ((STI.getFeatureBits()[R600::FeatureR600ALUInst]) &&
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((Desc.TSFlags & R600_InstFlag::OP1) ||
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Desc.TSFlags & R600_InstFlag::OP2)) {
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uint64_t ISAOpCode = Inst & (0x3FFULL << 39);
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Inst &= ~(0x3FFULL << 39);
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Inst |= ISAOpCode << 1;
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}
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Emit(Inst, OS);
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}
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}
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void R600MCCodeEmitter::Emit(uint32_t Value, raw_ostream &OS) const {
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support::endian::write(OS, Value, support::little);
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}
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void R600MCCodeEmitter::Emit(uint64_t Value, raw_ostream &OS) const {
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support::endian::write(OS, Value, support::little);
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}
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unsigned R600MCCodeEmitter::getHWReg(unsigned RegNo) const {
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return MRI.getEncodingValue(RegNo) & HW_REG_MASK;
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}
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uint64_t R600MCCodeEmitter::getMachineOpValue(const MCInst &MI,
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const MCOperand &MO,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const {
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if (MO.isReg()) {
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if (HAS_NATIVE_OPERANDS(MCII.get(MI.getOpcode()).TSFlags))
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return MRI.getEncodingValue(MO.getReg());
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return getHWReg(MO.getReg());
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}
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if (MO.isExpr()) {
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// We put rodata at the end of code section, then map the entire
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// code secetion as vtx buf. Thus the section relative address is the
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// correct one.
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// Each R600 literal instruction has two operands
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// We can't easily get the order of the current one, so compare against
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// the first one and adjust offset.
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const unsigned offset = (&MO == &MI.getOperand(0)) ? 0 : 4;
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Fixups.push_back(MCFixup::create(offset, MO.getExpr(), FK_SecRel_4, MI.getLoc()));
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return 0;
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}
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assert(MO.isImm());
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return MO.getImm();
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}
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#define ENABLE_INSTR_PREDICATE_VERIFIER
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#include "R600GenMCCodeEmitter.inc"
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