forked from OSchip/llvm-project
94620278a4
Currently in LLVM's cost model, a vectorized arithmetic instruction will have high cost if its type is split into multiple registers. However, this punishment is too heavy and unnecessary. The overhead of the split should not be on arithmetic instructions but instructions that implement the split. Note that during vectorization we have calculated the register pressure, and we only choose proper interleaving factor (and also vectorization factor) so that we don't use more registers than the maximum number. Here is a very simple example: if a vadd has the cost 1, and if we double VF so that we need two registers to perform it, then its cost will become 4 with the current implementation, which will prevent us to use larger VF. Differential revision: http://reviews.llvm.org/D15159 llvm-svn: 254671 |
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| .. | ||
| AssumptionCache | ||
| BasicAA | ||
| BlockFrequencyInfo | ||
| BranchProbabilityInfo | ||
| CFLAliasAnalysis | ||
| CallGraph | ||
| CostModel | ||
| Delinearization | ||
| DemandedBits | ||
| DependenceAnalysis | ||
| DivergenceAnalysis/NVPTX | ||
| Dominators | ||
| GlobalsModRef | ||
| LazyCallGraph | ||
| Lint | ||
| LoopAccessAnalysis | ||
| LoopInfo | ||
| MemoryDependenceAnalysis | ||
| PostDominators | ||
| RegionInfo | ||
| ScalarEvolution | ||
| ScopedNoAliasAA | ||
| TypeBasedAliasAnalysis | ||
| ValueTracking | ||