forked from OSchip/llvm-project
60 lines
1.9 KiB
LLVM
60 lines
1.9 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse2 | FileCheck %s --check-prefix=SSE --check-prefix=SSE2
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.2 | FileCheck %s --check-prefix=SSE --check-prefix=SSE42
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s --check-prefix=AVX --check-prefix=AVX1
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefix=AVX --check-prefix=AVX2
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; PR28925
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define <4 x i32> @test1(<4 x i1> %cond, <4 x i32> %x) {
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; SSE-LABEL: test1:
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; SSE: # BB#0:
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; SSE-NEXT: pslld $31, %xmm0
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; SSE-NEXT: psrad $31, %xmm0
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; SSE-NEXT: pandn %xmm1, %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: test1:
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; AVX: # BB#0:
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; AVX-NEXT: vpslld $31, %xmm0, %xmm0
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; AVX-NEXT: vpsrad $31, %xmm0, %xmm0
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; AVX-NEXT: vpandn %xmm1, %xmm0, %xmm0
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; AVX-NEXT: retq
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%r = select <4 x i1> %cond, <4 x i32> zeroinitializer, <4 x i32> %x
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ret <4 x i32> %r
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}
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define <4 x i32> @test2(<4 x float> %a, <4 x float> %b, <4 x i32> %x) {
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; SSE-LABEL: test2:
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; SSE: # BB#0:
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; SSE-NEXT: cmpneqps %xmm1, %xmm0
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; SSE-NEXT: andps %xmm2, %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: test2:
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; AVX: # BB#0:
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; AVX-NEXT: vcmpneqps %xmm1, %xmm0, %xmm0
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; AVX-NEXT: vandps %xmm2, %xmm0, %xmm0
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; AVX-NEXT: retq
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%cond = fcmp oeq <4 x float> %a, %b
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%r = select <4 x i1> %cond, <4 x i32> zeroinitializer, <4 x i32> %x
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ret <4 x i32> %r
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}
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define float @fsel(float %a, float %b, float %x) {
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; SSE-LABEL: fsel:
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; SSE: # BB#0:
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; SSE-NEXT: cmpeqss %xmm1, %xmm0
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; SSE-NEXT: andnps %xmm2, %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: fsel:
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; AVX: # BB#0:
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; AVX-NEXT: vcmpeqss %xmm1, %xmm0, %xmm0
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; AVX-NEXT: vandnps %xmm2, %xmm0, %xmm0
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; AVX-NEXT: retq
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%cond = fcmp oeq float %a, %b
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%sel = select i1 %cond, float 0.0, float %x
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ret float %sel
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}
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