forked from OSchip/llvm-project
133 lines
4.2 KiB
LLVM
133 lines
4.2 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=i686-unknown-unknown -mcpu=core-avx-i -mattr=+rdrnd | FileCheck %s --check-prefix=X86
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=core-avx-i -mattr=+rdrnd | FileCheck %s --check-prefix=X64
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declare {i16, i32} @llvm.x86.rdrand.16()
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declare {i32, i32} @llvm.x86.rdrand.32()
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define i32 @_rdrand16_step(i16* %random_val) {
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; X86-LABEL: _rdrand16_step:
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; X86: # BB#0:
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; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
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; X86-NEXT: rdrandw %ax
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; X86-NEXT: movzwl %ax, %edx
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; X86-NEXT: movl $1, %eax
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; X86-NEXT: cmovael %edx, %eax
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; X86-NEXT: movw %dx, (%ecx)
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; X86-NEXT: retl
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;
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; X64-LABEL: _rdrand16_step:
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; X64: # BB#0:
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; X64-NEXT: rdrandw %ax
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; X64-NEXT: movzwl %ax, %ecx
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; X64-NEXT: movl $1, %eax
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; X64-NEXT: cmovael %ecx, %eax
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; X64-NEXT: movw %cx, (%rdi)
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; X64-NEXT: retq
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%call = call {i16, i32} @llvm.x86.rdrand.16()
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%randval = extractvalue {i16, i32} %call, 0
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store i16 %randval, i16* %random_val
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%isvalid = extractvalue {i16, i32} %call, 1
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ret i32 %isvalid
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}
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define i32 @_rdrand32_step(i32* %random_val) {
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; X86-LABEL: _rdrand32_step:
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; X86: # BB#0:
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; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
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; X86-NEXT: rdrandl %edx
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; X86-NEXT: movl $1, %eax
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; X86-NEXT: cmovael %edx, %eax
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; X86-NEXT: movl %edx, (%ecx)
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; X86-NEXT: retl
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;
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; X64-LABEL: _rdrand32_step:
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; X64: # BB#0:
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; X64-NEXT: rdrandl %ecx
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; X64-NEXT: movl $1, %eax
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; X64-NEXT: cmovael %ecx, %eax
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; X64-NEXT: movl %ecx, (%rdi)
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; X64-NEXT: retq
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%call = call {i32, i32} @llvm.x86.rdrand.32()
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%randval = extractvalue {i32, i32} %call, 0
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store i32 %randval, i32* %random_val
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%isvalid = extractvalue {i32, i32} %call, 1
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ret i32 %isvalid
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}
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; Check that MachineCSE doesn't eliminate duplicate rdrand instructions.
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define i32 @CSE() nounwind {
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; X86-LABEL: CSE:
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; X86: # BB#0:
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; X86-NEXT: rdrandl %ecx
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; X86-NEXT: rdrandl %eax
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; X86-NEXT: addl %ecx, %eax
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; X86-NEXT: retl
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;
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; X64-LABEL: CSE:
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; X64: # BB#0:
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; X64-NEXT: rdrandl %ecx
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; X64-NEXT: rdrandl %eax
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; X64-NEXT: addl %ecx, %eax
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; X64-NEXT: retq
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%rand1 = tail call { i32, i32 } @llvm.x86.rdrand.32() nounwind
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%v1 = extractvalue { i32, i32 } %rand1, 0
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%rand2 = tail call { i32, i32 } @llvm.x86.rdrand.32() nounwind
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%v2 = extractvalue { i32, i32 } %rand2, 0
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%add = add i32 %v2, %v1
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ret i32 %add
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}
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; Check that MachineLICM doesn't hoist rdrand instructions.
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define void @loop(i32* %p, i32 %n) nounwind {
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; X86-LABEL: loop:
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; X86: # BB#0: # %entry
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; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X86-NEXT: testl %eax, %eax
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; X86-NEXT: je .LBB3_3
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; X86-NEXT: # BB#1: # %while.body.preheader
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; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
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; X86-NEXT: .p2align 4, 0x90
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; X86-NEXT: .LBB3_2: # %while.body
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; X86-NEXT: # =>This Inner Loop Header: Depth=1
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; X86-NEXT: rdrandl %edx
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; X86-NEXT: movl %edx, (%ecx)
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; X86-NEXT: leal 4(%ecx), %ecx
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; X86-NEXT: addl $-1, %eax
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; X86-NEXT: jne .LBB3_2
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; X86-NEXT: .LBB3_3: # %while.end
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; X86-NEXT: retl
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;
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; X64-LABEL: loop:
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; X64: # BB#0: # %entry
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; X64-NEXT: testl %esi, %esi
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; X64-NEXT: je .LBB3_2
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; X64-NEXT: .p2align 4, 0x90
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; X64-NEXT: .LBB3_1: # %while.body
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; X64-NEXT: # =>This Inner Loop Header: Depth=1
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; X64-NEXT: rdrandl %eax
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; X64-NEXT: movl %eax, (%rdi)
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; X64-NEXT: leaq 4(%rdi), %rdi
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; X64-NEXT: addl $-1, %esi
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; X64-NEXT: jne .LBB3_1
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; X64-NEXT: .LBB3_2: # %while.end
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; X64-NEXT: retq
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entry:
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%tobool1 = icmp eq i32 %n, 0
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br i1 %tobool1, label %while.end, label %while.body
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while.body: ; preds = %entry, %while.body
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%p.addr.03 = phi i32* [ %incdec.ptr, %while.body ], [ %p, %entry ]
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%n.addr.02 = phi i32 [ %dec, %while.body ], [ %n, %entry ]
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%dec = add nsw i32 %n.addr.02, -1
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%incdec.ptr = getelementptr inbounds i32, i32* %p.addr.03, i64 1
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%rand = tail call { i32, i32 } @llvm.x86.rdrand.32() nounwind
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%v1 = extractvalue { i32, i32 } %rand, 0
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store i32 %v1, i32* %p.addr.03, align 4
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%tobool = icmp eq i32 %dec, 0
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br i1 %tobool, label %while.end, label %while.body
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while.end: ; preds = %while.body, %entry
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ret void
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}
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