forked from OSchip/llvm-project
131 lines
6.5 KiB
LLVM
131 lines
6.5 KiB
LLVM
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=kaveri -disable-promote-alloca-to-vector < %s | FileCheck -check-prefix=GCN %s
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; This shows that the amount of LDS estimate is sensitive to the order
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; of the LDS globals.
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; Both of these functions use the same amount of LDS, but the total
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; changes depending on the visit order of first use.
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; The one with the suboptimal order resulting in extra padding exceeds
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; the desired limit
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; The padding estimate heuristic used by the promote alloca pass
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; is mostly determined by the order of the globals,
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; Raw usage = 1060 bytes
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; Rounded usage:
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; 292 + (4 pad) + 256 + (8 pad) + 512 = 1072
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; 512 + (0 pad) + 256 + (0 pad) + 292 = 1060
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; At default occupancy guess of 7, 2340 bytes available total.
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; 1280 need to be left to promote alloca
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; optimally packed, this requires
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@lds0 = internal unnamed_addr addrspace(3) global [32 x <4 x i32>] undef, align 16
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@lds2 = internal unnamed_addr addrspace(3) global [32 x i64] undef, align 8
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@lds1 = internal unnamed_addr addrspace(3) global [73 x i32] undef, align 4
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; GCN-LABEL: {{^}}promote_alloca_size_order_0:
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; GCN: workgroup_group_segment_byte_size = 2340
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define amdgpu_kernel void @promote_alloca_size_order_0(i32 addrspace(1)* nocapture %out, i32 addrspace(1)* nocapture %in, i32 %idx) #0 {
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entry:
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%stack = alloca [5 x i32], align 4, addrspace(5)
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%tmp0 = load i32, i32 addrspace(1)* %in, align 4
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%arrayidx1 = getelementptr inbounds [5 x i32], [5 x i32] addrspace(5)* %stack, i32 0, i32 %tmp0
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store i32 4, i32 addrspace(5)* %arrayidx1, align 4
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%arrayidx2 = getelementptr inbounds i32, i32 addrspace(1)* %in, i32 1
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%tmp1 = load i32, i32 addrspace(1)* %arrayidx2, align 4
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%arrayidx3 = getelementptr inbounds [5 x i32], [5 x i32] addrspace(5)* %stack, i32 0, i32 %tmp1
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store i32 5, i32 addrspace(5)* %arrayidx3, align 4
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%arrayidx10 = getelementptr inbounds [5 x i32], [5 x i32] addrspace(5)* %stack, i32 0, i32 0
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%tmp2 = load i32, i32 addrspace(5)* %arrayidx10, align 4
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store i32 %tmp2, i32 addrspace(1)* %out, align 4
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%arrayidx12 = getelementptr inbounds [5 x i32], [5 x i32] addrspace(5)* %stack, i32 0, i32 1
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%tmp3 = load i32, i32 addrspace(5)* %arrayidx12
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%arrayidx13 = getelementptr inbounds i32, i32 addrspace(1)* %out, i32 1
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store i32 %tmp3, i32 addrspace(1)* %arrayidx13
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%gep.lds1 = getelementptr inbounds [73 x i32], [73 x i32] addrspace(3)* @lds1, i32 0, i32 %idx
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store volatile i32 0, i32 addrspace(3)* %gep.lds1, align 4
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%gep.lds2 = getelementptr inbounds [32 x i64], [32 x i64] addrspace(3)* @lds2, i32 0, i32 %idx
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store volatile i64 0, i64 addrspace(3)* %gep.lds2, align 8
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%gep.lds0 = getelementptr inbounds [32 x <4 x i32>], [32 x <4 x i32>] addrspace(3)* @lds0, i32 0, i32 %idx
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store volatile <4 x i32> zeroinitializer, <4 x i32> addrspace(3)* %gep.lds0, align 16
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ret void
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}
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; GCN-LABEL: {{^}}promote_alloca_size_order_1:
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; GCN: workgroup_group_segment_byte_size = 2352
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define amdgpu_kernel void @promote_alloca_size_order_1(i32 addrspace(1)* nocapture %out, i32 addrspace(1)* nocapture %in, i32 %idx) #0 {
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entry:
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%stack = alloca [5 x i32], align 4, addrspace(5)
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%tmp0 = load i32, i32 addrspace(1)* %in, align 4
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%arrayidx1 = getelementptr inbounds [5 x i32], [5 x i32] addrspace(5)* %stack, i32 0, i32 %tmp0
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store i32 4, i32 addrspace(5)* %arrayidx1, align 4
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%arrayidx2 = getelementptr inbounds i32, i32 addrspace(1)* %in, i32 1
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%tmp1 = load i32, i32 addrspace(1)* %arrayidx2, align 4
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%arrayidx3 = getelementptr inbounds [5 x i32], [5 x i32] addrspace(5)* %stack, i32 0, i32 %tmp1
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store i32 5, i32 addrspace(5)* %arrayidx3, align 4
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%arrayidx10 = getelementptr inbounds [5 x i32], [5 x i32] addrspace(5)* %stack, i32 0, i32 0
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%tmp2 = load i32, i32 addrspace(5)* %arrayidx10, align 4
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store i32 %tmp2, i32 addrspace(1)* %out, align 4
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%arrayidx12 = getelementptr inbounds [5 x i32], [5 x i32] addrspace(5)* %stack, i32 0, i32 1
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%tmp3 = load i32, i32 addrspace(5)* %arrayidx12
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%arrayidx13 = getelementptr inbounds i32, i32 addrspace(1)* %out, i32 1
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store i32 %tmp3, i32 addrspace(1)* %arrayidx13
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%gep.lds0 = getelementptr inbounds [32 x <4 x i32>], [32 x <4 x i32>] addrspace(3)* @lds0, i32 0, i32 %idx
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store volatile <4 x i32> zeroinitializer, <4 x i32> addrspace(3)* %gep.lds0, align 16
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%gep.lds2 = getelementptr inbounds [32 x i64], [32 x i64] addrspace(3)* @lds2, i32 0, i32 %idx
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store volatile i64 0, i64 addrspace(3)* %gep.lds2, align 8
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%gep.lds1 = getelementptr inbounds [73 x i32], [73 x i32] addrspace(3)* @lds1, i32 0, i32 %idx
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store volatile i32 0, i32 addrspace(3)* %gep.lds1, align 4
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ret void
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}
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@lds3 = internal unnamed_addr addrspace(3) global [13 x i32] undef, align 4
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@lds4 = internal unnamed_addr addrspace(3) global [63 x <4 x i32>] undef, align 16
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; The guess from the alignment padding pushes this over the determined
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; size limit, so it isn't promoted
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; GCN-LABEL: {{^}}promote_alloca_align_pad_guess_over_limit:
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; GCN: workgroup_group_segment_byte_size = 1060
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define amdgpu_kernel void @promote_alloca_align_pad_guess_over_limit(i32 addrspace(1)* nocapture %out, i32 addrspace(1)* nocapture %in, i32 %idx) #0 {
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entry:
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%stack = alloca [5 x i32], align 4, addrspace(5)
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%tmp0 = load i32, i32 addrspace(1)* %in, align 4
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%arrayidx1 = getelementptr inbounds [5 x i32], [5 x i32] addrspace(5)* %stack, i32 0, i32 %tmp0
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store i32 4, i32 addrspace(5)* %arrayidx1, align 4
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%arrayidx2 = getelementptr inbounds i32, i32 addrspace(1)* %in, i32 1
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%tmp1 = load i32, i32 addrspace(1)* %arrayidx2, align 4
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%arrayidx3 = getelementptr inbounds [5 x i32], [5 x i32] addrspace(5)* %stack, i32 0, i32 %tmp1
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store i32 5, i32 addrspace(5)* %arrayidx3, align 4
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%arrayidx10 = getelementptr inbounds [5 x i32], [5 x i32] addrspace(5)* %stack, i32 0, i32 0
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%tmp2 = load i32, i32 addrspace(5)* %arrayidx10, align 4
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store i32 %tmp2, i32 addrspace(1)* %out, align 4
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%arrayidx12 = getelementptr inbounds [5 x i32], [5 x i32] addrspace(5)* %stack, i32 0, i32 1
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%tmp3 = load i32, i32 addrspace(5)* %arrayidx12
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%arrayidx13 = getelementptr inbounds i32, i32 addrspace(1)* %out, i32 1
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store i32 %tmp3, i32 addrspace(1)* %arrayidx13
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%gep.lds3 = getelementptr inbounds [13 x i32], [13 x i32] addrspace(3)* @lds3, i32 0, i32 %idx
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store volatile i32 0, i32 addrspace(3)* %gep.lds3, align 4
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%gep.lds4 = getelementptr inbounds [63 x <4 x i32>], [63 x <4 x i32>] addrspace(3)* @lds4, i32 0, i32 %idx
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store volatile <4 x i32> zeroinitializer, <4 x i32> addrspace(3)* %gep.lds4, align 16
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ret void
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}
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attributes #0 = { nounwind "amdgpu-flat-work-group-size"="64,64" "amdgpu-waves-per-eu"="1,7" }
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