llvm-project/llvm/test/MC
Anirudh Prasad f03c21df7b [SystemZ] Adding extra extended mnemonics for SystemZ target
This patch consists of the addition of some common additional
extended mnemonics to the SystemZ target.

- These are jnop, jct, jctg, jas, jasl, jxh, jxhg, jxle,
  jxleg, bru, brul, br*, br*l.
- These mnemonics and the instructions they map to are
  defined here, Chapter 4 - Branching with extended
  mnemonic codes.
- Except for jnop (which is a variant of brc 0, label), every
  other mnemonic is marked as a MnemonicAlias since there is
  already a "defined" instruction with the same encoding
  and/or condition mask values.
- brc 0, label doesn't have a defined extended mnemonic, thus
  jnop is defined using as an InstAlias. Furthermore, the
  applyMnemonicAliases function is called in the overridden
  parseInstruction function in SystemZAsmParser.cpp to ensure
  any mnemonic aliases are applied before any further
  processing on the instruction is done.

Reviewed By: uweigand

Differential Revision: https://reviews.llvm.org/D92185
2020-12-02 08:25:31 -05:00
..
AArch64 [ARM][AArch64] Adding Neoverse N2 CPU support 2020-11-25 11:42:54 +00:00
AMDGPU [AMDGPU][MC] Improved diagnostic messages 2020-11-23 16:15:05 +03:00
ARM [ARMAttributeParser] Correctly parse and print Tag_THUMB_ISA_use=3 2020-11-28 12:28:22 -08:00
AVR [AVRInstPrinter] printOperand: support llvm-objdump --print-imm-hex 2020-07-12 08:14:52 -07:00
AsmParser [MC/AsmParser] Fix use of Arm calling convention in target-agnostic test 2020-11-24 22:56:27 +00:00
BPF [test] llvm/test/: change llvm-objdump single-dash long options to double-dash options 2020-03-15 17:46:23 -07:00
COFF [test][MC] Use %python in llvm/test/MC/COFF/bigobj.py 2020-10-07 14:03:28 -04:00
Disassembler [ARM][AArch64] Adding Neoverse N2 CPU support 2020-11-25 11:42:54 +00:00
ELF [X86] Don't emit R_X86_64_[REX_]GOTPCRELX for a GOT load with an offset 2020-11-30 08:27:31 -08:00
Hexagon [llvm-readobj] Update tests because of changes in llvm-readobj behavior 2020-07-20 10:39:04 +01:00
Lanai
MSP430 [llvm-readobj] Update tests because of changes in llvm-readobj behavior 2020-07-20 10:39:04 +01:00
MachO llvm-dwarfdump: Dump address forms in their encoded length rather than always in 64 bits 2020-10-04 15:48:57 -07:00
Mips [MC][mips] Remove unused check prefixes. NFC 2020-11-13 14:31:13 +03:00
PowerPC [PowerPC] Allow a '%' prefix for registers in CFI directives 2020-11-19 18:19:51 -08:00
RISCV [RISCVAsmParser] Allow a SymbolRef operand to be a complex expression 2020-12-01 16:08:09 -08:00
Sparc [llvm-readobj] Update tests because of changes in llvm-readobj behavior 2020-07-20 10:39:04 +01:00
SystemZ [SystemZ] Adding extra extended mnemonics for SystemZ target 2020-12-02 08:25:31 -05:00
VE [VE] Add missing BCR format 2020-10-29 23:30:49 +09:00
WebAssembly [WebAssembly] Support select and block for reference types 2020-12-01 19:16:57 -08:00
X86 [X86] Support modifier @PLTOFF for R_X86_64_PLTOFF64 2020-12-01 08:39:01 -08:00