forked from OSchip/llvm-project
183 lines
4.9 KiB
LLVM
183 lines
4.9 KiB
LLVM
; Test vector sign extensions.
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;
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; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s
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; Test a v16i1->v16i8 extension.
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define <16 x i8> @f1(<16 x i8> %val) {
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; CHECK-LABEL: f1:
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; CHECK: veslb [[REG:%v[0-9]+]], %v24, 7
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; CHECK: vesrab %v24, [[REG]], 7
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; CHECK: br %r14
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%trunc = trunc <16 x i8> %val to <16 x i1>
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%ret = sext <16 x i1> %trunc to <16 x i8>
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ret <16 x i8> %ret
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}
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; Test a v8i1->v8i16 extension.
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define <8 x i16> @f2(<8 x i16> %val) {
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; CHECK-LABEL: f2:
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; CHECK: veslh [[REG:%v[0-9]+]], %v24, 15
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; CHECK: vesrah %v24, [[REG]], 15
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; CHECK: br %r14
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%trunc = trunc <8 x i16> %val to <8 x i1>
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%ret = sext <8 x i1> %trunc to <8 x i16>
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ret <8 x i16> %ret
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}
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; Test a v8i8->v8i16 extension.
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define <8 x i16> @f3(<8 x i16> %val) {
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; CHECK-LABEL: f3:
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; CHECK: veslh [[REG:%v[0-9]+]], %v24, 8
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; CHECK: vesrah %v24, [[REG]], 8
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; CHECK: br %r14
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%trunc = trunc <8 x i16> %val to <8 x i8>
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%ret = sext <8 x i8> %trunc to <8 x i16>
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ret <8 x i16> %ret
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}
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; Test a v4i1->v4i32 extension.
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define <4 x i32> @f4(<4 x i32> %val) {
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; CHECK-LABEL: f4:
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; CHECK: veslf [[REG:%v[0-9]+]], %v24, 31
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; CHECK: vesraf %v24, [[REG]], 31
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; CHECK: br %r14
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%trunc = trunc <4 x i32> %val to <4 x i1>
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%ret = sext <4 x i1> %trunc to <4 x i32>
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ret <4 x i32> %ret
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}
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; Test a v4i8->v4i32 extension.
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define <4 x i32> @f5(<4 x i32> %val) {
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; CHECK-LABEL: f5:
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; CHECK: veslf [[REG:%v[0-9]+]], %v24, 24
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; CHECK: vesraf %v24, [[REG]], 24
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; CHECK: br %r14
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%trunc = trunc <4 x i32> %val to <4 x i8>
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%ret = sext <4 x i8> %trunc to <4 x i32>
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ret <4 x i32> %ret
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}
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; Test a v4i16->v4i32 extension.
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define <4 x i32> @f6(<4 x i32> %val) {
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; CHECK-LABEL: f6:
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; CHECK: veslf [[REG:%v[0-9]+]], %v24, 16
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; CHECK: vesraf %v24, [[REG]], 16
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; CHECK: br %r14
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%trunc = trunc <4 x i32> %val to <4 x i16>
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%ret = sext <4 x i16> %trunc to <4 x i32>
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ret <4 x i32> %ret
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}
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; Test a v2i1->v2i64 extension.
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define <2 x i64> @f7(<2 x i64> %val) {
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; CHECK-LABEL: f7:
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; CHECK: veslg [[REG:%v[0-9]+]], %v24, 63
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; CHECK: vesrag %v24, [[REG]], 63
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; CHECK: br %r14
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%trunc = trunc <2 x i64> %val to <2 x i1>
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%ret = sext <2 x i1> %trunc to <2 x i64>
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ret <2 x i64> %ret
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}
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; Test a v2i8->v2i64 extension.
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define <2 x i64> @f8(<2 x i64> %val) {
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; CHECK-LABEL: f8:
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; CHECK: vsegb %v24, %v24
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; CHECK: br %r14
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%trunc = trunc <2 x i64> %val to <2 x i8>
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%ret = sext <2 x i8> %trunc to <2 x i64>
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ret <2 x i64> %ret
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}
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; Test a v2i16->v2i64 extension.
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define <2 x i64> @f9(<2 x i64> %val) {
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; CHECK-LABEL: f9:
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; CHECK: vsegh %v24, %v24
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; CHECK: br %r14
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%trunc = trunc <2 x i64> %val to <2 x i16>
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%ret = sext <2 x i16> %trunc to <2 x i64>
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ret <2 x i64> %ret
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}
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; Test a v2i32->v2i64 extension.
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define <2 x i64> @f10(<2 x i64> %val) {
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; CHECK-LABEL: f10:
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; CHECK: vsegf %v24, %v24
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; CHECK: br %r14
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%trunc = trunc <2 x i64> %val to <2 x i32>
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%ret = sext <2 x i32> %trunc to <2 x i64>
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ret <2 x i64> %ret
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}
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; Test an alternative v2i8->v2i64 extension.
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define <2 x i64> @f11(<2 x i64> %val) {
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; CHECK-LABEL: f11:
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; CHECK: vsegb %v24, %v24
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; CHECK: br %r14
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%shl = shl <2 x i64> %val, <i64 56, i64 56>
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%ret = ashr <2 x i64> %shl, <i64 56, i64 56>
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ret <2 x i64> %ret
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}
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; Test an alternative v2i16->v2i64 extension.
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define <2 x i64> @f12(<2 x i64> %val) {
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; CHECK-LABEL: f12:
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; CHECK: vsegh %v24, %v24
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; CHECK: br %r14
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%shl = shl <2 x i64> %val, <i64 48, i64 48>
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%ret = ashr <2 x i64> %shl, <i64 48, i64 48>
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ret <2 x i64> %ret
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}
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; Test an alternative v2i32->v2i64 extension.
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define <2 x i64> @f13(<2 x i64> %val) {
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; CHECK-LABEL: f13:
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; CHECK: vsegf %v24, %v24
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; CHECK: br %r14
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%shl = shl <2 x i64> %val, <i64 32, i64 32>
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%ret = ashr <2 x i64> %shl, <i64 32, i64 32>
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ret <2 x i64> %ret
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}
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; Test an extraction-based v2i8->v2i64 extension.
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define <2 x i64> @f14(<16 x i8> %val) {
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; CHECK-LABEL: f14:
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; CHECK: vsegb %v24, %v24
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; CHECK: br %r14
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%elt0 = extractelement <16 x i8> %val, i32 7
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%elt1 = extractelement <16 x i8> %val, i32 15
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%ext0 = sext i8 %elt0 to i64
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%ext1 = sext i8 %elt1 to i64
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%vec0 = insertelement <2 x i64> undef, i64 %ext0, i32 0
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%vec1 = insertelement <2 x i64> %vec0, i64 %ext1, i32 1
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ret <2 x i64> %vec1
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}
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; Test an extraction-based v2i16->v2i64 extension.
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define <2 x i64> @f15(<16 x i16> %val) {
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; CHECK-LABEL: f15:
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; CHECK: vsegh %v24, %v24
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; CHECK: br %r14
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%elt0 = extractelement <16 x i16> %val, i32 3
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%elt1 = extractelement <16 x i16> %val, i32 7
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%ext0 = sext i16 %elt0 to i64
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%ext1 = sext i16 %elt1 to i64
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%vec0 = insertelement <2 x i64> undef, i64 %ext0, i32 0
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%vec1 = insertelement <2 x i64> %vec0, i64 %ext1, i32 1
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ret <2 x i64> %vec1
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}
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; Test an extraction-based v2i32->v2i64 extension.
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define <2 x i64> @f16(<16 x i32> %val) {
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; CHECK-LABEL: f16:
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; CHECK: vsegf %v24, %v24
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; CHECK: br %r14
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%elt0 = extractelement <16 x i32> %val, i32 1
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%elt1 = extractelement <16 x i32> %val, i32 3
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%ext0 = sext i32 %elt0 to i64
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%ext1 = sext i32 %elt1 to i64
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%vec0 = insertelement <2 x i64> undef, i64 %ext0, i32 0
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%vec1 = insertelement <2 x i64> %vec0, i64 %ext1, i32 1
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ret <2 x i64> %vec1
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}
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