Hal Finkel f11bc761d8 [PowerPC] Include the permutation cost for unaligned vector loads ... Pre-P8, when we generate code for unaligned vector loads (for Altivec and QPX types), even when accounting for the combining that takes place for multiple consecutive such loads, there is at least one load instructions and one permutation for each load. Make sure the cost reported reflects the cost of the permutes as well. llvm-svn: 246807		2015-09-03 21:23:18 +00:00
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AArch64	[opaque pointer type] Add textual IR support for explicit type parameter to load instruction	2015-02-27 21:17:42 +00:00
ARM	[CostModel][ARM] Increase cost of insert/extract operations	2015-08-17 15:57:05 +00:00
PowerPC	[PowerPC] Include the permutation cost for unaligned vector loads	2015-09-03 21:23:18 +00:00
X86	[X86][SSE] Vectorize i64 ASHR operations	2015-07-29 20:31:45 +00:00
no_info.ll	Roll forward r243250	2015-07-26 19:10:03 +00:00