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llvm-project/llvm/test/CodeGen/MIR
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Matthias Braun 716b43306b MachineVerifier: Add missing linebreak 
MachineInstr::print() with SkipOppers==true does not produce a
linebreak, so we have to do that in MachineVerifier::report().

llvm-svn: 252551
 		2015-11-09 23:59:29 +00:00
..
AArch64 MIR Serialization: Use the global value syntax for global value memory operands. 2015-08-20 00:20:03 +00:00
AMDGPU MIR Serialization: Change MIR syntax - use custom syntax for MBBs. 2015-08-13 23:10:16 +00:00
ARM MIR Serialization: Serialize the '.cfi_same_value' CFI directive. 2015-08-14 21:55:58 +00:00
Generic MIR Serialization: Change MIR syntax - use custom syntax for MBBs. 2015-08-13 23:10:16 +00:00
Mips [mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE. 2015-10-15 14:34:23 +00:00
NVPTX MIR Serialization: Change MIR syntax - use custom syntax for MBBs. 2015-08-13 23:10:16 +00:00
PowerPC Fix PR 24724 - The implicit register verifier shouldn't assume certain operand 2015-09-10 14:04:34 +00:00
X86 MachineVerifier: Add missing linebreak 2015-11-09 23:59:29 +00:00
lit.local.cfg Resubmit r237954 (MIR Serialization: print and parse LLVM IR using MIR format). 2015-05-27 18:02:19 +00:00