llvm-project/llvm/test/CodeGen/Mips/GlobalISel
Craig Topper b1c304c494 [CodeGen] Try to make the print of memory operand alignment a little more user friendly.
Memory operands store a base alignment that does not factor in
the effect of the offset on the alignment.

Previously the printing code only printed the base alignment if
it was different than the size. If there is an offset, the reader
would need to figure out the effective alignment themselves. This
has confused me before and someone else was recently confused on
IRC.

This patch prints the possibly offset adjusted alignment if it is
different than the size. And prints the base alignment if it is
different than the alignment. The MIR parser has been updated to
read basealign in addition to align.

Reviewed By: arsenm

Differential Revision: https://reviews.llvm.org/D94344
2021-01-11 19:58:47 -08:00
..
instruction-select [MIPS GlobalISel] Select 4 byte unaligned load and store 2020-02-19 11:57:06 +01:00
irtranslator OpaquePtr: Bulk update tests to use typed sret 2020-11-20 17:58:26 -05:00
legalizer [CodeGen] Try to make the print of memory operand alignment a little more user friendly. 2021-01-11 19:58:47 -08:00
llvm-ir OpaquePtr: Bulk update tests to use typed sret 2020-11-20 17:58:26 -05:00
mips-prelegalizer-combiner
regbankselect [CodeGen] Try to make the print of memory operand alignment a little more user friendly. 2021-01-11 19:58:47 -08:00