llvm-project/llvm/test/CodeGen
David Green 7b6f760fcd [ARM] MVE vector lane interleaving
MVE does not have a single sext/zext or trunc instruction that takes the
bottom half of a vector and extends to a full width, like NEON has with
MOVL. Instead it is expected that this happens through top/bottom
instructions. So the MVE equivalent VMOVLT/B instructions take either
the even or odd elements of the input and extend them to the larger
type, producing a vector with half the number of elements each of double
the bitwidth. As there is no simple instruction for a normal extend, we
often have to expand sext/zext/trunc into a series of lane moves (or
stack loads/stores, which we do not do yet).

This pass takes vector code that starts at truncs, looks for
interconnected blobs of operations that end with sext/zext and
transforms them by adding shuffles so that the lanes are interleaved and
the MVE VMOVL/VMOVN instructions can be used. This is done pre-ISel so
that it can work across basic blocks.

This initial version of the pass just handles a limited set of
instructions, not handling constants or splats or FP, which can all come
as extensions to this base.

Differential Revision: https://reviews.llvm.org/D95804
2021-03-28 19:34:58 +01:00
..
AArch64 AArch64/GlobalISel: Remove IR section from test 2021-03-28 11:12:59 -04:00
AMDGPU [AMDGPU] Use reductions instead of scans in the atomic optimizer 2021-03-26 15:38:14 +00:00
ARC
ARM [ARM] MVE vector lane interleaving 2021-03-28 19:34:58 +01:00
AVR [AVR] Fix lifeness issues in the AVR backend 2021-03-04 14:04:39 +01:00
BPF BPF: add extern func to data sections if specified 2021-03-25 16:03:29 -07:00
Generic [XCore][Test] XFAIL tests requiring 8-byte stack alignment. 2021-03-24 09:12:53 +00:00
Hexagon [Hexagon] Add support for named registers cs0 and cs1 2021-03-18 09:53:22 -05:00
Inputs
Lanai
M68k [DAG] computeKnownBits - add ISD::MULHS/MULHU/SMUL_LOHI/UMUL_LOHI handling 2021-03-19 16:02:31 +00:00
MIR MIR: Fix missing serialization for HasTailCall 2021-03-21 13:14:04 -04:00
MSP430
Mips Test cases for rem-seteq fold with illegal types 2021-03-12 16:28:04 +02:00
NVPTX [NVPTX] CUDA does provide malloc/free since compute capability 2.X 2021-03-15 22:45:56 -05:00
PowerPC [PowerPC] auto-generate complete testchecks; NFC 2021-03-25 15:52:39 -04:00
RISCV [RISCV] Add test case for mulhsu. 2021-03-28 11:03:39 -07:00
SPARC [LegalizeTypes] Improve ExpandIntRes_XMULO codegen. 2021-03-01 09:54:32 -08:00
SystemZ [SystemZ] Reimplement the i8/i16 compare-and-swap logic. 2021-03-03 14:04:32 -06:00
Thumb [ARM] Regenerate some test checks. NFC 2021-03-24 15:34:34 +00:00
Thumb2 [ARM] MVE vector lane interleaving 2021-03-28 19:34:58 +01:00
VE [test] Fix CodeGen/VE/Scalar tests 2021-03-02 15:30:44 -08:00
WebAssembly [WebAssembly] Rename WasmLimits::Initial to ::Minimum. NFC. 2021-03-24 09:10:11 +01:00
WinCFGuard
WinEH
X86 Reapply "OpaquePtr: Turn inalloca into a type attribute" 2021-03-28 13:35:21 -04:00
XCore [CodeGen] Report a normal instead of fatal error for label redefinition 2021-03-09 10:54:41 +00:00