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Yuanfang Chen 647c3f4e47 [Support] make report_fatal_error `abort` instead of `exit` 
Summary:
This patch could be treated as a rebase of D33960. It also fixes PR35547.
A fix for `llvm/test/Other/close-stderr.ll` is proposed in D68164. Seems
the consensus is that the test is passing by chance and I'm not
sure how important it is for us. So it is removed like in D33960 for now.
The rest of the test fixes are just adding `--crash` flag to `not` tool.

** The reason it fixes PR35547 is

`exit` does cleanup including calling class destructor whereas `abort`
does not do any cleanup. In multithreading environment such as ThinLTO or JIT,
threads may share states which mostly are ManagedStatic<>. If faulting thread
tearing down a class when another thread is using it, there are chances of
memory corruption. This is bad 1. It will stop error reporting like pretty
stack printer; 2. The memory corruption is distracting and nondeterministic in
terms of error message, and corruption type (depending one the timing, it
could be double free, heap free after use, etc.).

Reviewers: rnk, chandlerc, zturner, sepavloff, MaskRay, espindola

Reviewed By: rnk, MaskRay

Subscribers: wuzish, jholewinski, qcolombet, dschuff, jyknight, emaste, sdardis, nemanjai, jvesely, nhaehnle, sbc100, arichardson, jgravelle-google, aheejin, kbarton, fedor.sergeev, asb, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, jrtc27, zzheng, edward-jones, atanasyan, rogfer01, MartinMosbeck, brucehoult, the_o, PkmX, jocewei, jsji, lenary, s.egerton, pzheng, cfe-commits, MaskRay, filcab, davide, MatzeB, mehdi_amini, hiraditya, steven_wu, dexonsmith, rupprecht, seiya, llvm-commits

Tags: #llvm, #clang

Differential Revision: https://reviews.llvm.org/D67847
 		2020-01-15 17:05:13 -08:00
..
GlobalISel [Support] make report_fatal_error `abort` instead of `exit` 2020-01-15 17:05:13 -08:00
32-bit-local-address-space.ll AMDGPU: Write LDS objects out as global symbols in code generation 2019-06-25 11:52:30 +00:00
InlineAsmCrash.ll
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README
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accvgpr-copy.mir [AMDGPU] gfx908 mfma support 2019-07-11 21:19:33 +00:00
add-debug.ll
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add.i16.ll [AMDGPU] Fix typo in SIInstrInfo::memOpsHaveSameBasePtr 2019-12-17 18:54:27 +00:00
add.ll AMDGPU: Select VOP3 form of add 2019-05-08 22:09:57 +00:00
add.v2i16.ll AMDGPU: Undo sub x, c canonicalization for v2i16 2019-06-19 23:37:43 +00:00
add3.ll [AMDGPU] gfx1010 core wave32 changes 2019-06-20 15:08:34 +00:00
add_i1.ll [AMDGPU] gfx1010 core wave32 changes 2019-06-20 15:08:34 +00:00
add_i64.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
add_i128.ll
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add_shl.ll [AMDGPU] gfx1010 core wave32 changes 2019-06-20 15:08:34 +00:00
addrspacecast-captured.ll AMDGPU: Fix using old address spaces in some tests 2018-12-05 17:34:59 +00:00
addrspacecast-constantexpr.ll [FunctionAttrs] Annotate "willreturn" for intrinsics 2019-07-28 06:09:56 +00:00
addrspacecast.ll AMDGPU: Enable code object v3 for AMDHSA only 2018-11-15 02:32:43 +00:00
adjust-writemask-invalid-copy.ll AMDGPU: Convert test cases to the dimension-aware intrinsics 2018-06-21 13:37:19 +00:00
agpr-register-count.ll [AMDGPU] separate accounting for agprs 2019-10-02 00:26:58 +00:00
alignbit-pat.ll
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alloca.ll AMDGPU: Remove remnants of old address space mapping 2018-08-31 05:49:54 +00:00
always-uniform.ll
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amdgcn-ieee.ll AMDGPU: Remove dx10-clamp from subtarget features 2019-03-29 19:14:54 +00:00
amdgcn.bitcast.ll AMDGPU: Make v4i16/v4f16 legal 2018-06-15 15:15:46 +00:00
amdgcn.private-memory.ll AMDGPU: Change boolean content type to 0 or 1 2019-11-15 13:43:47 +05:30
amdgpu-alias-analysis.ll AMDGPU: Improve alias analysis for GDS 2019-07-17 11:22:19 +00:00
amdgpu-codegenprepare-fdiv.ll
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amdgpu-codegenprepare-i16-to-i32.ll [AMDGPU] Early expansion of 32 bit udiv/urem 2018-06-28 15:59:18 +00:00
amdgpu-codegenprepare-idiv.ll [IRBuilder] Update IRBuilder::CreateFNeg(...) to return a UnaryOperator 2019-10-14 15:35:01 +00:00
amdgpu-codegenprepare-mul24.ll AMDGPU: Introduce a flag to disable mul24 intrinsic formation 2019-08-24 22:14:41 +00:00
amdgpu-function-calls-option.ll AMDGPU: Enable function calls by default 2019-02-28 00:40:32 +00:00
amdgpu-inline.ll [AMDGPU] Tune inlining parameters for AMDGPU target (part 2) 2019-11-19 16:33:16 +03:00
amdgpu-mul24-knownbits.ll Fix for AMDGPU MUL_I24 known bits calculation 2019-12-16 10:25:57 +00:00
amdgpu-shader-calling-convention.ll
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amdgpu-unroll-threshold.ll [AMDGPU] Add attribute for target loop unroll threshold default 2019-11-21 09:47:28 +00:00
amdgpu.private-memory.ll AMDGPU: Switch backend default max workgroup size to 1024 2019-11-13 07:11:02 +05:30
amdgpu.work-item-intrinsics.deprecated.ll
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amdhsa-trap-num-sgprs.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
amdpal-cs.ll
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amdpal-es.ll
…
amdpal-gs.ll
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amdpal-hs.ll
…
amdpal-ls.ll
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amdpal-msgpack-cs.ll [AMDGPU] Added MsgPack format PAL metadata 2019-03-20 18:47:21 +00:00
amdpal-msgpack-es.ll [AMDGPU] Added MsgPack format PAL metadata 2019-03-20 18:47:21 +00:00
amdpal-msgpack-gs.ll [AMDGPU] Added MsgPack format PAL metadata 2019-03-20 18:47:21 +00:00
amdpal-msgpack-hs.ll [AMDGPU] Added MsgPack format PAL metadata 2019-03-20 18:47:21 +00:00
amdpal-msgpack-ls.ll [AMDGPU] Added MsgPack format PAL metadata 2019-03-20 18:47:21 +00:00
amdpal-msgpack-ps.ll [AMDGPU] Added MsgPack format PAL metadata 2019-03-20 18:47:21 +00:00
amdpal-msgpack-psenable.ll [AMDGPU] Added MsgPack format PAL metadata 2019-03-20 18:47:21 +00:00
amdpal-msgpack-vs.ll [AMDGPU] Added MsgPack format PAL metadata 2019-03-20 18:47:21 +00:00
amdpal-ps.ll
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amdpal-psenable.ll
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amdpal-vs.ll
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amdpal.ll [AMDGPU] Fix CS scratch setup on pre-GCN3 ASICs 2019-02-08 15:41:11 +00:00
amdpal_scratch_mergedshader.ll [AMDGPU] Enable LICM in the BE pipeline 2018-06-29 16:26:53 +00:00
and-gcn.ll
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and.ll [DAGCombine] Prune unnused nodes. 2019-03-29 17:35:56 +00:00
and_or.ll [AMDGPU] gfx1010 core wave32 changes 2019-06-20 15:08:34 +00:00
andorbitset.ll [AMDGPU] Shrink scalar AND, OR, XOR instructions 2018-12-07 15:33:21 +00:00
andorn2.ll [AMDGPU] Add and update scalar instructions 2018-11-29 16:05:38 +00:00
andorxorinvimm.ll [AMDGPU] Shrink scalar AND, OR, XOR instructions 2018-12-07 15:33:21 +00:00
annotate-kernel-features-hsa-call.ll AMDGPU: Handle "uniform-work-group-size" attribute (fix for RADV) 2019-03-07 00:54:04 +00:00
annotate-kernel-features-hsa.ll AMDGPU: Add intrinsics for address space identification 2019-09-05 02:20:39 +00:00
annotate-kernel-features.ll
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anonymous-gv.ll
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any_extend_vector_inreg.ll
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anyext.ll
…
are-loads-from-same-base-ptr.ll AMDGPU: Fix areLoadsFromSameBasePtr for DS atomics 2019-03-27 15:41:00 +00:00
array-ptr-calc-i32.ll AMDGPU: Switch backend default max workgroup size to 1024 2019-11-13 07:11:02 +05:30
array-ptr-calc-i64.ll
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ashr.v2i16.ll [FileCheck] Add -allow-deprecated-dag-overlap to failing llvm tests 2018-07-11 20:25:49 +00:00
at-least-one-def-value-assert.mir [Support] make report_fatal_error `abort` instead of `exit` 2020-01-15 17:05:13 -08:00
atomic_cmp_swap_local.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
atomic_load_add.ll [AMDGPU] Add an AMDGPU specific atomic optimizer. 2018-10-08 15:49:19 +00:00
atomic_load_local.ll AMDGPU: Add patterns for i32/i64 local atomic load/store 2018-06-22 08:39:52 +00:00
atomic_load_sub.ll [AMDGPU] Add an AMDGPU specific atomic optimizer. 2018-10-08 15:49:19 +00:00
atomic_optimizations_buffer.ll [AMDGPU] gfx10 atomic optimizer changes. 2019-08-23 10:07:43 +00:00
atomic_optimizations_global_pointer.ll [AMDGPU] gfx10 atomic optimizer changes. 2019-08-23 10:07:43 +00:00
atomic_optimizations_local_pointer.ll [AMDGPU] Invert the handling of skip insertion. 2020-01-15 15:18:16 +05:30
atomic_optimizations_pixelshader.ll [AMDGPU] Invert the handling of skip insertion. 2020-01-15 15:18:16 +05:30
atomic_optimizations_raw_buffer.ll [AMDGPU] gfx10 atomic optimizer changes. 2019-08-23 10:07:43 +00:00
atomic_optimizations_struct_buffer.ll [AMDGPU] gfx10 atomic optimizer changes. 2019-08-23 10:07:43 +00:00
atomic_store_local.ll AMDGPU: Add patterns for i32/i64 local atomic load/store 2018-06-22 08:39:52 +00:00
atomicrmw-nand.ll [AMDGPU] Come back patch for the 'Assign register class for cross block values according to the divergence.' 2019-10-14 12:01:10 +00:00
attr-amdgpu-flat-work-group-size-v3.ll AMDGPU Reduce reported maximum group size to 1024 2019-11-13 06:34:28 +05:30
attr-amdgpu-flat-work-group-size.ll AMDGPU Reduce reported maximum group size to 1024 2019-11-13 06:34:28 +05:30
attr-amdgpu-num-sgpr.ll [AMDGPU] Remove -amdgpu-spill-sgpr-to-smem. 2019-10-18 21:48:22 +00:00
attr-amdgpu-num-vgpr.ll
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attr-amdgpu-waves-per-eu.ll
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attr-unparseable.ll
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barrier-elimination.ll
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basic-branch.ll [AMDGPU] Remove -amdgpu-spill-sgpr-to-smem. 2019-10-18 21:48:22 +00:00
basic-call-return.ll
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basic-loop.ll
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bfe-combine.ll
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bfe-patterns.ll [AMDGPU] Divergence driven instruction selection. Part 1. 2018-09-21 10:31:22 +00:00
bfe_uint.ll
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bfi_int.ll AMDGPU: Scalarize vector argument types to calls 2018-07-31 19:05:14 +00:00
bfm.ll
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big_alu.ll
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bitcast-constant-to-vector.ll [MachineScheduler] Reduce reordering due to mem op clustering 2020-01-14 19:19:02 +00:00
bitcast-v4f16-v4i16.ll AMDGPU: Add patterns for v4i16/v4f16 -> v4i16/v4f16 bitcasts 2018-12-19 22:53:33 +00:00
bitcast-vector-extract.ll IR: Add immarg attribute 2019-03-12 21:02:54 +00:00
bitreverse-inline-immediates.ll
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bitreverse.ll [AMDGPU] SIFoldOperands should not fold register acrocc the EXEC definition 2019-09-30 15:31:17 +00:00
br_cc.f16.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
branch-condition-and.ll [AMDGPU] Invert the handling of skip insertion. 2020-01-15 15:18:16 +05:30
branch-relax-bundle.ll
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branch-relax-spill.ll [Support] make report_fatal_error `abort` instead of `exit` 2020-01-15 17:05:13 -08:00
branch-relaxation-debug-info.ll AMDGPU: Skip debug instructions in assert 2019-04-22 19:14:26 +00:00
branch-relaxation-inst-size-gfx10.ll MC: Allow getMaxInstLength to depend on the subtarget 2019-05-22 16:28:41 +00:00
branch-relaxation.ll [AMDGPU] Invert the handling of skip insertion. 2020-01-15 15:18:16 +05:30
branch-uniformity.ll [AMDGPU] Come back patch for the 'Assign register class for cross block values according to the divergence.' 2019-10-14 12:01:10 +00:00
break-smem-soft-clauses.mir [AMDGPU] gfx1010 VMEM and SMEM implementation 2019-04-30 22:08:23 +00:00
break-vmem-soft-clauses.mir [AMDGPU] Extend buffer intrinsics with swizzling 2019-10-02 17:22:36 +00:00
bswap.ll [codegen,amdgpu] Enhance MIR DIE and re-arrange it for AMDGPU. 2020-01-14 19:26:15 -05:00
buffer-intrinsics-mmo-offsets.ll Revert "Revert "[MIR] Target specific MIR formating and parsing"" 2020-01-08 20:03:29 -08:00
buffer-schedule.ll
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bug-vopc-commute.ll AMDGPU: Convert tests away from llvm.SI.load.const 2019-01-17 22:47:26 +00:00
build-vector-insert-elt-infloop.ll AMDGPU: Move d16 load matching to preprocess step 2019-03-08 20:58:11 +00:00
build-vector-packed-partial-undef.ll AMDGPU: Always use s33 for global scratch wave offset 2019-06-20 21:58:24 +00:00
build_vector.ll
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bundle-latency.mir [AMDGPU] Model distance to instruction in bundle 2020-01-14 01:18:59 -08:00
byval-frame-setup.ll [MachineScheduler] Reduce reordering due to mem op clustering 2020-01-14 19:19:02 +00:00
call-argument-types.ll [MachineScheduler] Reduce reordering due to mem op clustering 2020-01-14 19:19:02 +00:00
call-constant.ll AMDGPU: Don't error on calls to null or undef 2019-10-20 07:46:04 +00:00
call-constexpr.ll [AMDGPU] Packed thread ids in function call ABI 2019-06-28 01:52:13 +00:00
call-encoding.ll
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call-graph-register-usage.ll [AMDGPU] Add handling of 160 bit registers in analyzeResourceUsage 2019-11-06 15:47:32 -08:00
call-preserved-registers.ll [AMDGPU] Created a sub-register class for the return address operand in the return instruction. 2019-07-09 16:48:42 +00:00
call-return-types.ll [AMDGPU] Support for v3i32/v3f32 2019-03-21 12:01:21 +00:00
call-skip.ll [AMDGPU] Invert the handling of skip insertion. 2020-01-15 15:18:16 +05:30
call-to-kernel-undefined.ll [Support] make report_fatal_error `abort` instead of `exit` 2020-01-15 17:05:13 -08:00
call-to-kernel.ll [Support] make report_fatal_error `abort` instead of `exit` 2020-01-15 17:05:13 -08:00
call-waitcnt.ll AMDGPU: Make s34 the FP register 2019-07-08 19:03:38 +00:00
call-waw-waitcnt.mir AMDGPU: Avoid overwriting saved PC 2019-10-28 10:02:22 -07:00
call_fs.ll
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callee-frame-setup.ll [AMDGPU] Created a sub-register class for the return address operand in the return instruction. 2019-07-09 16:48:42 +00:00
callee-special-input-sgprs.ll [AMDGPU] Created a sub-register class for the return address operand in the return instruction. 2019-07-09 16:48:42 +00:00
callee-special-input-vgprs.ll AMDGPU: Allow getMemOperandWithOffset to analyze stack accesses 2019-09-05 23:54:35 +00:00
calling-conventions.ll AMDGPU: Don't assert on v4f16 arguments to shader calling conventions 2019-07-25 13:55:07 +00:00
captured-frame-index.ll
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cayman-loop-bug.ll
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cc-sgpr-limit.ll [AMDGPU] Adjust number of SGPRs available in Calling Convention 2019-08-28 15:00:45 +00:00
cc-sgpr-over-limit.ll [Support] make report_fatal_error `abort` instead of `exit` 2020-01-15 17:05:13 -08:00
cf-loop-on-constant.ll
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cf-stack-bug.ll
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cf_end.ll
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cgp-addressing-modes-flat.ll
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cgp-addressing-modes.ll AMDGPU: Split flat offsets that don't fit in DAG 2019-10-20 17:34:44 +00:00
cgp-bitfield-extract.ll [DAGCombiner] re-enable truncation of binops 2018-12-08 16:07:38 +00:00
chain-hi-to-lo.ll [MachineScheduler] Reduce reordering due to mem op clustering 2020-01-14 19:19:02 +00:00
clamp-modifier.ll AMDGPU: Improve hack for packing conversion ops 2018-08-01 20:13:58 +00:00
clamp-omod-special-case.mir [AMDGPU] Extend buffer intrinsics with swizzling 2019-10-02 17:22:36 +00:00
clamp.ll AMDGPU: Remove dx10-clamp from subtarget features 2019-03-29 19:14:54 +00:00
cluster-flat-loads-postra.mir [AMDGPU] gfx1010 VMEM and SMEM implementation 2019-04-30 22:08:23 +00:00
cluster-flat-loads.mir [AMDGPU] gfx1010 VMEM and SMEM implementation 2019-04-30 22:08:23 +00:00
cndmask-no-def-vcc.ll [DAG] add undef simplifications for select nodes 2018-11-18 17:36:23 +00:00
coalescer-extend-pruned-subrange.mir AMDGPU: Use SGPR_128 instead of SReg_128 for vregs 2019-10-10 07:11:33 +00:00
coalescer-identical-values-undef.mir AMDGPU: Use SGPR_128 instead of SReg_128 for vregs 2019-10-10 07:11:33 +00:00
coalescer-subranges-another-copymi-not-live.mir AMDGPU: Use SGPR_128 instead of SReg_128 for vregs 2019-10-10 07:11:33 +00:00
coalescer-subranges-another-prune-error.mir AMDGPU: Use SGPR_128 instead of SReg_128 for vregs 2019-10-10 07:11:33 +00:00
coalescer-subranges-prune-kill-copy.mir Fix register coalescer failure to prune value 2019-05-21 19:32:41 +00:00
coalescer-subreg-join.mir AMDGPU: Use SGPR_128 instead of SReg_128 for vregs 2019-10-10 07:11:33 +00:00
coalescer-subregjoin-fullcopy.mir AMDGPU: Use SGPR_128 instead of SReg_128 for vregs 2019-10-10 07:11:33 +00:00
coalescer-with-subregs-bad-identical.mir AMDGPU: Use SGPR_128 instead of SReg_128 for vregs 2019-10-10 07:11:33 +00:00
coalescer_distribute.ll AMDGPU: Don't use spir_kernel in a test 2018-07-05 17:01:29 +00:00
coalescer_remat.ll
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coalescing-with-subregs-in-loop-bug.mir AMDGPU: Fix missing scc implicit def on s_andn2_b64_term 2019-03-27 16:58:22 +00:00
code-object-v3.ll [llvm-readobj] Change -long-option to --long-option in tests. NFC 2019-05-01 05:27:20 +00:00
codegen-prepare-addrmode-sext.ll
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collapse-endcf-broken.mir AMDGPU: Add additional MIR tests for exec mask optimizations 2019-03-27 16:58:30 +00:00
collapse-endcf.ll [AMDGPU] Invert the handling of skip insertion. 2020-01-15 15:18:16 +05:30
collapse-endcf.mir [AMDGPU] Extend buffer intrinsics with swizzling 2019-10-02 17:22:36 +00:00
collapse-endcf2.mir [AMDGPU] Extend buffer intrinsics with swizzling 2019-10-02 17:22:36 +00:00
combine-and-sext-bool.ll
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combine-cond-add-sub.ll Revert "AMDGPU: Try to commute sub of boolean ext" 2019-12-13 12:49:06 +00:00
combine-ftrunc.ll
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combine_vloads.ll AMDGPU: Remove remnants of old address space mapping 2018-08-31 05:49:54 +00:00
comdat.ll [llvm-readobj] Change -long-option to --long-option in tests. NFC 2019-05-01 05:27:20 +00:00
commute-compares.ll [AMDGPU] Preliminary patch for divergence driven instruction selection. Immediate selection predicate changed 2018-09-11 11:56:50 +00:00
commute-shifts.ll [AMDGPU] Come back patch for the 'Assign register class for cross block values according to the divergence.' 2019-10-14 12:01:10 +00:00
commute_modifiers.ll [AMDGPU] Preliminary patch for divergence driven instruction selection. Immediate selection predicate changed 2018-09-11 11:56:50 +00:00
complex-folding.ll
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computeKnownBits-scalar-to-vector-crash.ll [SelectionDAG] Don't pass on DemandedElts when handling SCALAR_TO_VECTOR 2018-12-07 09:18:44 +00:00
computeNumSignBits-mul.ll [AMDGPU] Update autogenerated checks 2019-12-17 16:48:02 +00:00
concat_vectors.ll DAG: Fix creating concat_vectors with illegal type 2018-06-15 12:09:15 +00:00
constant-address-space-32bit.ll AMDGPU: Fix folding immediate into readfirstlane through reg_sequence 2019-06-19 20:44:15 +00:00
constant-fold-imm-immreg.mir AMDGPU: Use SGPR_128 instead of SReg_128 for vregs 2019-10-10 07:11:33 +00:00
constant-fold-mi-operands.ll AMDGPU: Explicitly define a triple for some tests 2019-06-17 19:25:57 +00:00
control-flow-fastregalloc.ll [AMDGPU] Invert the handling of skip insertion. 2020-01-15 15:18:16 +05:30
control-flow-optnone.ll [StructurizeCFG] Enable -structurizecfg-relaxed-uniform-regions by default 2019-08-06 14:30:19 +00:00
convergent-inlineasm.ll [AMDGPU] Invert the handling of skip insertion. 2020-01-15 15:18:16 +05:30
copy-illegal-type.ll [codegen,amdgpu] Enhance MIR DIE and re-arrange it for AMDGPU. 2020-01-14 19:26:15 -05:00
copy-to-reg.ll
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couldnt-join-subrange-3.mir AMDGPU: Use SGPR_128 instead of SReg_128 for vregs 2019-10-10 07:11:33 +00:00
cross-block-use-is-not-abi-copy.ll AMDGPU: Fix crash from inconsistent register types for v3i16/v3f16 2019-08-27 17:51:56 +00:00
cse-phi-incoming-val.ll [AMDGPU] Invert the handling of skip insertion. 2020-01-15 15:18:16 +05:30
csr-gfx10.ll AMDGPU: Fix not marking new gfx10 SGPRs as CSRs 2019-05-21 23:23:05 +00:00
ctlz.ll [AMDGPU] Regenerate CTLZ tests for an upcoming patch 2019-05-31 15:06:14 +00:00
ctlz_zero_undef.ll [AMDGPU] Preliminary patch for divergence driven instruction selection. Immediate selection predicate changed 2018-09-11 11:56:50 +00:00
ctpop.ll [AMDGPU] Fix typo in SIInstrInfo::memOpsHaveSameBasePtr 2019-12-17 18:54:27 +00:00
ctpop16.ll [AMDGPU] Fix typo in SIInstrInfo::memOpsHaveSameBasePtr 2019-12-17 18:54:27 +00:00
ctpop64.ll [AMDGPU] Divergence driven instruction selection. Part 1. 2018-09-21 10:31:22 +00:00
cttz_zero_undef.ll
…
cube.ll
…
cvt_f32_ubyte.ll [MachineScheduler] Reduce reordering due to mem op clustering 2020-01-14 19:19:02 +00:00
cvt_flr_i32_f32.ll
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cvt_rpi_i32_f32.ll
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dag-divergence.ll AMDGPU: Fix DAG divergence not reporting flat loads 2018-09-04 18:58:19 +00:00
dagcomb-shuffle-vecextend-non2.ll
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dagcombine-reassociate-bug.ll
…
dagcombine-select.ll [AMDGPU] Early expansion of 32 bit udiv/urem 2018-06-28 15:59:18 +00:00
dagcombine-setcc-select.ll [AMDGPU] Automatically generate various tests. NFC 2019-08-23 17:58:49 +00:00
dagcombiner-bug-illegal-vec4-int-to-fp.ll
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dce-disjoint-intervals.mir AMDGPU: Use SGPR_128 instead of SReg_128 for vregs 2019-10-10 07:11:33 +00:00
dead-lane.mir [AMDGPU] gfx1010 VMEM and SMEM implementation 2019-04-30 22:08:23 +00:00
dead-machine-elim-after-dead-lane.ll [codegen,amdgpu] Enhance MIR DIE and re-arrange it for AMDGPU. 2020-01-14 19:26:15 -05:00
dead_copy.mir [AMDGPU] gfx1010 VMEM and SMEM implementation 2019-04-30 22:08:23 +00:00
debug-value-scheduler-crash.mir [AMDGPU] gfx1010 VMEM and SMEM implementation 2019-04-30 22:08:23 +00:00
debug-value.ll AMDGPU: Remove remnants of old address space mapping 2018-08-31 05:49:54 +00:00
debug-value2.ll AMDGPU: Decompose all values to 32-bit pieces for calling conventions 2019-07-19 13:57:44 +00:00
debug.ll [AMDGPU] Fix +DumpCode to print an entry label for the first function 2019-06-27 08:19:28 +00:00
default-fp-mode.ll AMDGPU: Drop remnants of byval support for shaders 2019-07-12 20:12:17 +00:00
detect-dead-lanes.mir AMDGPU: Use SGPR_128 instead of SReg_128 for vregs 2019-10-10 07:11:33 +00:00
directive-amdgcn-target.ll AMDGPU: Make sram-ecc off by default for Vega20 2019-03-29 12:04:18 +00:00
disable_form_clauses.ll [AMDGPU] Added target-specific attribute amdgpu-max-memory-clause 2019-05-30 18:46:34 +00:00
disconnected-predset-break-bug.ll
…
div_i128.ll [Support] make report_fatal_error `abort` instead of `exit` 2020-01-15 17:05:13 -08:00
diverge-extra-formal-args.ll
…
diverge-interp-mov-lower.ll
…
diverge-switch-default.ll [AMDGPU] gfx1010 wave32 icmp/fcmp intrinsic changes for wave32 2019-06-13 23:47:36 +00:00
divergence-at-use.ll [AMDGPU] Add amdgpu_kernel for consistency with other tests 2019-07-29 11:48:17 +00:00
divergent-branch-uniform-condition.ll [AMDGPU] Invert the handling of skip insertion. 2020-01-15 15:18:16 +05:30
divrem24-assume.ll [IRBuilder] Update IRBuilder::CreateFNeg(...) to return a UnaryOperator 2019-10-14 15:35:01 +00:00
dpp_combine.ll [AMDGPU] link dpp pseudos and real instructions on gfx10 2019-10-11 22:03:36 +00:00
dpp_combine.mir [AMDGPU] Disallow dpp combining for dpp instructions without Src2 operand (when Src2 is required) 2019-10-25 21:30:37 +03:00
drop-mem-operand-move-smrd.ll
…
ds-combine-large-stride.ll
…
ds-combine-with-dependence.ll AMDGPU: Correct DS implementation of areLoadsFromSameBasePtr 2019-03-08 20:30:50 +00:00
ds-negative-offset-addressing-mode-loop.ll AMDGPU: Increase vcc liveness scan threshold 2019-10-20 17:44:17 +00:00
ds-sub-offset.ll AMDGPU: Write LDS objects out as global symbols in code generation 2019-06-25 11:52:30 +00:00
ds_read2.ll [MachineScheduler] Reduce reordering due to mem op clustering 2020-01-14 19:19:02 +00:00
ds_read2_offset_order.ll
…
ds_read2_superreg.ll
…
ds_read2st64.ll
…
ds_write2.ll AMDGPU: Write LDS objects out as global symbols in code generation 2019-06-25 11:52:30 +00:00
ds_write2st64.ll [AMDGPU] Disable SReg Global LD/ST, perf regression 2018-11-30 18:29:17 +00:00
dynamic_stackalloc.ll AMDGPU: Remove remnants of old address space mapping 2018-08-31 05:49:54 +00:00
early-if-convert-cost.ll [AMDGPU] Support for v3i32/v3f32 2019-03-21 12:01:21 +00:00
early-if-convert.ll AMDGPU: Fix capitalized register names in asm constraints 2019-06-14 21:16:06 +00:00
early-inline-alias.ll
…
early-inline.ll Reapply "AMDGPU: Force inlining if LDS global address is used" 2018-07-10 14:03:41 +00:00
early-tailduplicator-nophis.mir TailDuplication: Clear NoPHIs property 2019-12-27 14:06:31 -05:00
elf-header-flags-mach.ll [AMDGPU] gfx908 target 2019-07-09 18:10:06 +00:00
elf-header-flags-sram-ecc.ll [AMDGPU] gfx908 target 2019-07-09 18:10:06 +00:00
elf-header-flags-xnack.ll [llvm-readobj] Change -long-option to --long-option in tests. NFC 2019-05-01 05:27:20 +00:00
elf-header-osabi.ll [llvm-readobj] Change -long-option to --long-option in tests. NFC 2019-05-01 05:27:20 +00:00
elf-notes.ll [llvm-readobj] Change -long-option to --long-option in tests. NFC 2019-05-01 05:27:20 +00:00
elf.ll [llvm-readobj] Change -long-option to --long-option in tests. NFC 2019-05-01 05:27:20 +00:00
elf.metadata.ll [llvm-readobj] Change -long-option to --long-option in tests. NFC 2019-05-01 05:27:20 +00:00
elf.r600.ll [llvm-readobj] Change -long-option to --long-option in tests. NFC 2019-05-01 05:27:20 +00:00
else.ll [AMDGPU] Invert the handling of skip insertion. 2020-01-15 15:18:16 +05:30
empty-function.ll
…
enable-no-signed-zeros-fp-math.ll Migrate some more fadd and fsub cases away from UnsafeFPMath control to utilize NoSignedZerosFPMath options control 2019-07-31 21:57:28 +00:00
endcf-loop-header.ll
…
endpgm-dce.mir AMDGPU: Add some tests for inlineasm behavior 2019-05-21 23:23:12 +00:00
enqueue-kernel.ll [AMDGPU] Change enqueue kernel handle type 2018-06-13 17:31:51 +00:00
exceed-max-sgprs.ll
…
extend-bit-ops-i16.ll
…
extload-align.ll AMDGPU: Remove remnants of old address space mapping 2018-08-31 05:49:54 +00:00
extload-private.ll
…
extload.ll
…
extract-lowbits.ll [AMDGPU] Divergence driven instruction selection. Part 1. 2018-09-21 10:31:22 +00:00
extract-subvector-equal-length.ll AMDGPU: Remove optnone from a test 2019-10-19 01:34:59 +00:00
extract-subvector.ll [DAGCombine] Replace `getIntPtrConstant()` with `getVectorIdxTy()`. 2020-01-14 17:03:05 -05:00
extract-vector-elt-build-vector-combine.ll
…
extract_subvector_vec4_vec3.ll Revert "Revert "[MIR] Target specific MIR formating and parsing"" 2020-01-08 20:03:29 -08:00
extract_vector_dynelt.ll AMDGPU: Change boolean content type to 0 or 1 2019-11-15 13:43:47 +05:30
extract_vector_elt-f16.ll AMDGPU: Remove remnants of old address space mapping 2018-08-31 05:49:54 +00:00
extract_vector_elt-f64.ll [AMDGPU] combine extractelement into several selects 2018-11-13 21:18:21 +00:00
extract_vector_elt-i8.ll [FileCheck] Add -allow-deprecated-dag-overlap to failing llvm tests 2018-07-11 20:25:49 +00:00
extract_vector_elt-i16.ll AMDGPU: Remove remnants of old address space mapping 2018-08-31 05:49:54 +00:00
extract_vector_elt-i64.ll [AMDGPU] combine extractelement into several selects 2018-11-13 21:18:21 +00:00
extractelt-to-trunc.ll [AMDGPU] Regenerate extractelt->truncate test. 2019-04-19 09:49:04 +00:00
fabs.f16.ll [AMDGPU] Divergence driven instruction selection. Part 1. 2018-09-21 10:31:22 +00:00
fabs.f64.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
fabs.ll [AMDGPU] Come back patch for the 'Assign register class for cross block values according to the divergence.' 2019-10-14 12:01:10 +00:00
fadd-fma-fmul-combine.ll [DAGCombiner] Check term use before applying aggressive FSUB optimisations 2019-12-23 09:37:58 +09:00
fadd.f16.ll [AMDGPU] Fix typo in SIInstrInfo::memOpsHaveSameBasePtr 2019-12-17 18:54:27 +00:00
fadd.ll Utilize new SDNode flag functionality to expand current support for fadd 2018-06-18 23:44:59 +00:00
fadd64.ll
…
fcanonicalize-elimination.ll [AMDGPU] Fix for vector element insertion 2019-02-01 16:51:09 +00:00
fcanonicalize.f16.ll DAG: Handle odd vector sizes in calling conv splitting 2018-09-10 11:49:23 +00:00
fcanonicalize.ll [AMDGPU] gfx1010 tests. NFC. 2019-05-13 19:30:06 +00:00
fceil.ll
…
fceil64.ll [AMDGPU] Add and update scalar instructions 2018-11-29 16:05:38 +00:00
fcmp-cnd.ll
…
fcmp-cnde-int-args.ll
…
fcmp.f16.ll [FileCheck] Add -allow-deprecated-dag-overlap to failing llvm tests 2018-07-11 20:25:49 +00:00
fcmp.ll
…
fcmp64.ll
…
fconst64.ll
…
fcopysign.f16.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
fcopysign.f32.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
fcopysign.f64.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
fdiv.f16.ll [AMDGPU] gfx1010: use fmac instructions 2019-05-04 04:20:37 +00:00
fdiv.f64.ll
…
fdiv.ll [DAGCombiner] Improve division estimation of floating points. 2019-09-12 07:51:24 +00:00
fdiv32-to-rcp-folding.ll [AMDGPU] Come back patch for the 'Assign register class for cross block values according to the divergence.' 2019-10-14 12:01:10 +00:00
fdot2.ll [AMDGPU] gfx1011/gfx1012 targets 2019-06-14 00:33:31 +00:00
fence-barrier.ll AMDGPU: Increase vcc liveness scan threshold 2019-10-20 17:44:17 +00:00
fetch-limits.r600.ll
…
fetch-limits.r700+.ll
…
fexp.ll [AMDGPU] Clean up update_llc_test_checks CodeGen tests 2019-10-24 17:35:33 -04:00
ffloor.f64.ll Migrate some more fadd and fsub cases away from UnsafeFPMath control to utilize NoSignedZerosFPMath options control 2019-07-31 21:57:28 +00:00
ffloor.ll
…
fix-sgpr-copies.mir AMDGPU: Fix infinite searches in SIFixSGPRCopies 2019-10-15 19:59:45 +00:00
fix-vgpr-copies.mir [Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing 2019-09-11 11:16:48 +00:00
fix-wwm-vgpr-copy.ll [AMDGPU] Fix a weird WWM intrinsic issue. 2019-01-29 14:28:17 +00:00
flat-address-space.ll AMDGPU: Split flat offsets that don't fit in DAG 2019-10-20 17:34:44 +00:00
flat-error-unsupported-gpu-hsa.ll [Support] make report_fatal_error `abort` instead of `exit` 2020-01-15 17:05:13 -08:00
flat-for-global-subtarget-feature.ll AMDGPU: Enable code object v3 for AMDHSA only 2018-11-15 02:32:43 +00:00
flat-load-clustering.mir [Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing 2019-09-11 11:16:48 +00:00
flat-offset-bug.ll [AMDGPU] gfx1010 VMEM and SMEM implementation 2019-04-30 22:08:23 +00:00
flat-scratch-reg.ll AMDGPU: Enable code object v3 for AMDHSA only 2018-11-15 02:32:43 +00:00
flat_atomics.ll Allow FP types for atomicrmw xchg 2019-01-17 10:49:01 +00:00
flat_atomics_i64.ll Allow FP types for atomicrmw xchg 2019-01-17 10:49:01 +00:00
floor.ll
…
fma-combine.ll
…
fma.f64.ll [AMDGPU] Improve fma.f64 test. NFC. 2019-09-25 18:50:34 +00:00
fma.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
fmac.sdwa.ll [AMDGPU] Enable v4f16 and above for v_pk_fma instructions 2019-07-29 08:15:10 +00:00
fmad.ll
…
fmax.ll
…
fmax3.f64.ll DAG: Change behavior of fminnum/fmaxnum nodes 2018-10-22 16:27:27 +00:00
fmax3.ll DAG: Change behavior of fminnum/fmaxnum nodes 2018-10-22 16:27:27 +00:00
fmax_legacy.f16.ll [DAGCombine] narrowInsertExtractVectorBinOp - add CONCAT_VECTORS support 2019-07-11 14:45:03 +00:00
fmax_legacy.f64.ll AMDGPU: Cleanup min/max legacy tests 2018-08-12 19:29:53 +00:00
fmax_legacy.ll DAG: Change behavior of fminnum/fmaxnum nodes 2018-10-22 16:27:27 +00:00
fmaxnum.f64.ll
…
fmaxnum.ll DAG: Change behavior of fminnum/fmaxnum nodes 2018-10-22 16:27:27 +00:00
fmaxnum.r600.ll AMDGPU: Split amdgcn/r600 fminnum/fmaxnum tests 2018-07-31 20:38:42 +00:00
fmed3.ll AMDGPU: Don't form fmed3 if it will require materialization 2018-09-18 02:34:54 +00:00
fmin.ll
…
fmin3.ll [AMDGPU] Ban i8 min3 promotion. 2019-03-19 15:50:24 +00:00
fmin_fmax_legacy.amdgcn.ll DAG: Change behavior of fminnum/fmaxnum nodes 2018-10-22 16:27:27 +00:00
fmin_legacy.f16.ll [DAGCombine] narrowInsertExtractVectorBinOp - add CONCAT_VECTORS support 2019-07-11 14:45:03 +00:00
fmin_legacy.f64.ll AMDGPU: Cleanup min/max legacy tests 2018-08-12 19:29:53 +00:00
fmin_legacy.ll [AMDGPU] Come back patch for the 'Assign register class for cross block values according to the divergence.' 2019-10-14 12:01:10 +00:00
fminnum.f64.ll DAG: Change behavior of fminnum/fmaxnum nodes 2018-10-22 16:27:27 +00:00
fminnum.ll DAG: Change behavior of fminnum/fmaxnum nodes 2018-10-22 16:27:27 +00:00
fminnum.r600.ll AMDGPU: Split amdgcn/r600 fminnum/fmaxnum tests 2018-07-31 20:38:42 +00:00
fmul-2-combine-multi-use.ll [AMDGPU] Come back patch for the 'Assign register class for cross block values according to the divergence.' 2019-10-14 12:01:10 +00:00
fmul.f16.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
fmul.ll
…
fmul64.ll
…
fmuladd.f16.ll [AMDGPU] Fix test checks 2019-10-07 10:57:41 +00:00
fmuladd.f32.ll
…
fmuladd.f64.ll
…
fmuladd.v2f16.ll
…
fnearbyint.ll
…
fneg-combines.ll AMDGPU/GlobalISel: Select G_FABS/G_FNEG 2019-09-10 17:19:46 +00:00
fneg-combines.si.ll AMDGPU: Address todo for handling 1/(2 pi) 2018-08-15 21:03:55 +00:00
fneg-fabs.f16.ll [DAGCombine] GetNegatedExpression - constant float vector support (PR42105) 2019-06-11 09:44:33 +00:00
fneg-fabs.f64.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
fneg-fabs.ll [AMDGPU] Come back patch for the 'Assign register class for cross block values according to the divergence.' 2019-10-14 12:01:10 +00:00
fneg-fold-legalize-dag-increase-insts.ll DAG: Stop trying to fold FP -(x-y) -> y-x in getNode with nsz 2019-12-31 22:49:51 -05:00
fneg.f16.ll
…
fneg.f64.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
fneg.ll [AMDGPU] Come back patch for the 'Assign register class for cross block values according to the divergence.' 2019-10-14 12:01:10 +00:00
fold-cndmask.mir [AMDGPU] Asm/disasm v_cndmask_b32_e64 with abs/neg source modifiers 2019-03-18 19:25:39 +00:00
fold-fi-mubuf.mir [AMDGPU] Extend buffer intrinsics with swizzling 2019-10-02 17:22:36 +00:00
fold-fi-operand-shrink.mir AMDGPU: Support shrinking add with FI in SIFoldOperands 2019-05-03 15:21:53 +00:00
fold-fmul-to-neg-abs.ll
…
fold-imm-copy.mir [AMDGPU] Skip additional folding on the same operand. 2019-10-24 11:30:22 -04:00
fold-imm-f16-f32.mir AMDGPU: Use SGPR_128 instead of SReg_128 for vregs 2019-10-10 07:11:33 +00:00
fold-immediate-operand-shrink-with-carry.mir [AMDGPU] Asm/disasm clamp modifier on vop3 int arithmetic 2019-03-18 19:35:44 +00:00
fold-immediate-operand-shrink.mir AMDGPU: Replace shrunk instruction with dummy implicit_def 2019-05-03 14:40:10 +00:00
fold-immediate-output-mods.mir [AMDGPU] Extend buffer intrinsics with swizzling 2019-10-02 17:22:36 +00:00
fold-implicit-operand.mir [AMDGPU] Add support for immediate operand for S_ENDPGM 2019-03-12 09:52:58 +00:00
fold-multiple.mir AMDGPU: Use SGPR_128 instead of SReg_128 for vregs 2019-10-10 07:11:33 +00:00
fold-operands-order.mir
…
fold-operands-remove-m0-redef.mir AMDGPU: Erase redundant redefs of m0 in SIFoldOperands 2019-10-21 19:53:46 +00:00
fold-over-exec.mir [AMDGPU] SIFoldOperands should not fold register acrocc the EXEC definition 2019-09-30 15:31:17 +00:00
fold-readlane.mir [AMDGPU] Fix to 'Fold readlane from copy of SGPR or imm' 2019-08-13 18:57:55 +00:00
fold-reload-into-m0.mir AMDGPU: Disallow spill folding with m0 copies 2019-10-30 14:56:33 -07:00
fold-sgpr-copy.mir [AMDGPU] Enable SGPR copy folding 2019-10-25 15:08:30 -07:00
fold-sgpr-multi-imm.mir AMDGPU: Avoid folding 2 constant operands into an SALU operation 2019-12-04 10:25:34 +00:00
fold-vgpr-copy.mir [AMDGPU] Allow folding of sgpr to vgpr copy 2019-10-23 18:42:48 -07:00
fold_acc_copy_into_valu.mir [AMDGPU] Fix illegal agpr use by VALU 2019-10-02 23:23:46 +00:00
force-alwaysinline-lds-global-address-codegen.ll AMDGPU: Always run AMDGPUAlwaysInline 2018-10-03 02:47:25 +00:00
force-alwaysinline-lds-global-address.ll AMDGPU: Enable function calls by default 2019-02-28 00:40:32 +00:00
fp-atomic-to-s_denormmode.mir [AMDGPU] hazard recognizer for fp atomic to s_denorm_mode 2019-06-21 16:30:14 +00:00
fp-classify.ll AMDGPU: Combine and of seto/setuo and fp_class 2018-08-10 18:58:56 +00:00
fp16_to_fp32.ll
…
fp16_to_fp64.ll
…
fp32_to_fp16.ll
…
fp_to_sint.f64.ll
…
fp_to_sint.ll [FileCheck] Add -allow-deprecated-dag-overlap to failing llvm tests 2018-07-11 20:25:49 +00:00
fp_to_uint.f64.ll
…
fp_to_uint.ll [FileCheck] Add -allow-deprecated-dag-overlap to failing llvm tests 2018-07-11 20:25:49 +00:00
fpext-free.ll AMDGPU: Fix V_FMA_F16 selection on GFX9 2018-11-19 21:10:16 +00:00
fpext.f16.ll [FileCheck] Add -allow-deprecated-dag-overlap to failing llvm tests 2018-07-11 20:25:49 +00:00
fpext.ll
…
fpow.ll AMDGPU: Fix legalizing f16 fpow 2020-01-06 17:21:51 -05:00
fptosi.f16.ll
…
fptoui.f16.ll
…
fptrunc.f16.ll
…
fptrunc.ll [SelectionDAG] Add support for FP_ROUND in WidenVectorOperand. 2019-10-30 15:18:21 +00:00
fract.f64.ll
…
fract.ll
…
frame-index-elimination.ll [MachineScheduler] Reduce reordering due to mem op clustering 2020-01-14 19:19:02 +00:00
frame-lowering-entry-all-sgpr-used.mir [AMDGPU] Skip calculating callee saved registers for entry function. 2019-07-11 23:53:30 +00:00
frame-lowering-fp-adjusted.mir Migrate function attribute "no-frame-pointer-elim" to "frame-pointer"="all" as cleanups after D56351 2019-12-24 15:57:33 -08:00
frem.ll
…
fsqrt.f64.ll
…
fsqrt.ll
…
fsub.f16.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
fsub.ll [AMDGPU] Come back patch for the 'Assign register class for cross block values according to the divergence.' 2019-10-14 12:01:10 +00:00
fsub64.ll
…
ftrunc.f64.ll [AMDGPU] Add and update scalar instructions 2018-11-29 16:05:38 +00:00
ftrunc.ll
…
function-args.ll AMDGPU: Don't fix emergency stack slot at offset 0 2019-06-05 22:37:50 +00:00
function-call-relocs.ll [AMDGPU] Support emitting GOT relocations for function calls 2019-02-04 20:00:07 +00:00
function-returns.ll AMDGPU: Add some function return test cases 2019-07-19 16:45:48 +00:00
gds-atomic.ll AMDGPU: Support GDS atomics 2019-07-01 17:17:45 +00:00
gep-address-space.ll [AMDGPU] Shrink scalar AND, OR, XOR instructions 2018-12-07 15:33:21 +00:00
gfx10-vop-literal.ll [AMDGPU] gfx10 tests. NFC. 2019-06-20 16:29:40 +00:00
gfx902-without-xnack.ll AMDGPU: Enable code object v3 for AMDHSA only 2018-11-15 02:32:43 +00:00
global-atomics-fp.ll AMDGPU: Select global atomicrmw fadd 2019-11-06 16:06:38 -08:00
global-constant.ll Partially revert D61491 "AMDGPU: Be explicit about whether the high-word in SI_PC_ADD_REL_OFFSET is 0" 2019-09-02 14:40:57 +00:00
global-directive.ll
…
global-extload-i16.ll
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global-load-store-atomics.mir AMDGPU: Use SGPR_128 instead of SReg_128 for vregs 2019-10-10 07:11:33 +00:00
global-saddr.ll AMDGPU: Split flat offsets that don't fit in DAG 2019-10-20 17:34:44 +00:00
global-smrd-unknown.ll
…
global-variable-relocs.ll
…
global_atomics.ll AMDGPU: Split flat offsets that don't fit in DAG 2019-10-20 17:34:44 +00:00
global_atomics_i64.ll AMDGPU: Split flat offsets that don't fit in DAG 2019-10-20 17:34:44 +00:00
global_smrd.ll [AMDGPU] Fix typo in SIInstrInfo::memOpsHaveSameBasePtr 2019-12-17 18:54:27 +00:00
global_smrd_cfg.ll Revert [MBP] Disable aggressive loop rotate in plain mode 2019-08-29 19:03:58 +00:00
gv-const-addrspace.ll
…
gv-offset-folding.ll
…
gws-hazards.mir Reapply "AMDGPU: Add ds_gws_init / ds_gws_barrier intrinsics" 2019-06-19 19:55:27 +00:00
half.ll [AMDGPU] Support for v3i32/v3f32 2019-03-21 12:01:21 +00:00
hazard-buffer-store-v-interp.mir [AMDGPU] Extend buffer intrinsics with swizzling 2019-10-02 17:22:36 +00:00
hazard-hidden-bundle.mir [AMDGPU] Extend buffer intrinsics with swizzling 2019-10-02 17:22:36 +00:00
hazard-in-bundle.mir [AMDGPU] gfx1010: small test change for wave32. NFC 2019-06-13 19:05:04 +00:00
hazard-inlineasm.mir [AMDGPU] gfx1010 VMEM and SMEM implementation 2019-04-30 22:08:23 +00:00
hazard-kill.mir [AMDGPU] gfx1010 VMEM and SMEM implementation 2019-04-30 22:08:23 +00:00
hazard.mir [Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing 2019-09-11 11:16:48 +00:00
hoist-cond.ll [AMDGPU] Invert the handling of skip insertion. 2020-01-15 15:18:16 +05:30
hsa-default-device.ll
…
hsa-fp-mode.ll AMDGPU: Remove dx10-clamp from subtarget features 2019-03-29 19:14:54 +00:00
hsa-func-align.ll [llvm-readobj] Change -long-option to --long-option in tests. NFC 2019-05-01 05:27:20 +00:00
hsa-func.ll [llvm-readobj] Change -long-option to --long-option in tests. NFC 2019-05-01 05:27:20 +00:00
hsa-globals.ll AMDGPU: Fix tests using old number for constant address space 2018-09-10 02:54:25 +00:00
hsa-group-segment.ll
…
hsa-metadata-deduce-ro-arg-v3.ll [llvm-readobj] Change -long-option to --long-option in tests. NFC 2019-05-01 05:27:20 +00:00
hsa-metadata-deduce-ro-arg.ll [llvm-readobj] Change -long-option to --long-option in tests. NFC 2019-05-01 05:27:20 +00:00
hsa-metadata-enqueue-kernel-v3.ll [llvm-readobj] Change -long-option to --long-option in tests. NFC 2019-05-01 05:27:20 +00:00
hsa-metadata-enqueue-kernel.ll [llvm-readobj] Change -long-option to --long-option in tests. NFC 2019-05-01 05:27:20 +00:00
hsa-metadata-from-llvm-ir-full-v3.ll [AMDGPU] add support for hostcall buffer pointer as hidden kernel argument 2019-11-20 15:53:55 +05:30
hsa-metadata-from-llvm-ir-full.ll [AMDGPU] add support for hostcall buffer pointer as hidden kernel argument 2019-11-20 15:53:55 +05:30
hsa-metadata-hidden-args-v3.ll [AMDGPU] Added a new metadata for multi grid sync implicit argument 2019-07-05 16:05:17 +00:00
hsa-metadata-hidden-args.ll [AMDGPU] Added a new metadata for multi grid sync implicit argument 2019-07-05 16:05:17 +00:00
hsa-metadata-hostcall-absent-v3.ll [AMDGPU] add support for hostcall buffer pointer as hidden kernel argument 2019-11-20 15:53:55 +05:30
hsa-metadata-hostcall-absent.ll [AMDGPU] add support for hostcall buffer pointer as hidden kernel argument 2019-11-20 15:53:55 +05:30
hsa-metadata-hostcall-present-v3.ll [AMDGPU] add support for hostcall buffer pointer as hidden kernel argument 2019-11-20 15:53:55 +05:30
hsa-metadata-hostcall-present.ll [AMDGPU] add support for hostcall buffer pointer as hidden kernel argument 2019-11-20 15:53:55 +05:30
hsa-metadata-images-v3.ll [llvm-readobj] Change -long-option to --long-option in tests. NFC 2019-05-01 05:27:20 +00:00
hsa-metadata-images.ll [llvm-readobj] Change -long-option to --long-option in tests. NFC 2019-05-01 05:27:20 +00:00
hsa-metadata-invalid-ocl-version-1-v3.ll [llvm-readobj] Change -long-option to --long-option in tests. NFC 2019-05-01 05:27:20 +00:00
hsa-metadata-invalid-ocl-version-1.ll [llvm-readobj] Change -long-option to --long-option in tests. NFC 2019-05-01 05:27:20 +00:00
hsa-metadata-invalid-ocl-version-2-v3.ll [llvm-readobj] Change -long-option to --long-option in tests. NFC 2019-05-01 05:27:20 +00:00
hsa-metadata-invalid-ocl-version-2.ll [llvm-readobj] Change -long-option to --long-option in tests. NFC 2019-05-01 05:27:20 +00:00
hsa-metadata-invalid-ocl-version-3-v3.ll [llvm-readobj] Change -long-option to --long-option in tests. NFC 2019-05-01 05:27:20 +00:00
hsa-metadata-invalid-ocl-version-3.ll [llvm-readobj] Change -long-option to --long-option in tests. NFC 2019-05-01 05:27:20 +00:00
hsa-metadata-kernel-code-props-v3.ll AMDGPU: Switch backend default max workgroup size to 1024 2019-11-13 07:11:02 +05:30
hsa-metadata-kernel-code-props.ll AMDGPU: Switch backend default max workgroup size to 1024 2019-11-13 07:11:02 +05:30
hsa-metadata-wavefrontsize.ll [AMDGPU] gfx1010 wave32 metadata 2019-06-17 16:48:56 +00:00
hsa-note-no-func.ll [AMDGPU] gfx908 target 2019-07-09 18:10:06 +00:00
hsa.ll [AMDGPU] gfx10 tests. NFC. 2019-06-20 16:29:40 +00:00
huge-private-buffer.ll [AMDGPU] gfx1010 core wave32 changes 2019-06-20 15:08:34 +00:00
i1-copies-rpo.mir AMDGPU: Make fixing i1 copies robust against re-ordering 2019-06-27 16:56:44 +00:00
i1-copy-from-loop.ll [AMDGPU] Fix emitIfBreak CF lowering: use temp reg to make register coalescer life easier. 2019-11-26 18:59:37 +03:00
i1-copy-implicit-def.ll
…
i1-copy-phi-uniform-branch.ll [AMDGPU] Come back patch for the 'Assign register class for cross block values according to the divergence.' 2019-10-14 12:01:10 +00:00
i1-copy-phi.ll [SelectionDAG] Enhance the simplification of `copyto` from `implicit-def`. 2019-05-27 18:26:29 +00:00
i1_copy_phi_with_phi_incoming_value.mir [AMDGPU] Fix Vreg_1 PHI lowering in SILowerI1Copies. 2019-10-26 14:37:45 +05:30
i8-to-double-to-float.ll
…
icmp-select-sete-reverse-args.ll
…
icmp.i16.ll
…
icmp64.ll
…
idiv-licm.ll AMDGPU: Run AMDGPUCodeGenPrepare after scalar opts 2019-08-27 00:08:31 +00:00
idot2.ll [AMDGPU] Fix typo in SIInstrInfo::memOpsHaveSameBasePtr 2019-12-17 18:54:27 +00:00
idot4s.ll [AMDGPU] Fix typo in SIInstrInfo::memOpsHaveSameBasePtr 2019-12-17 18:54:27 +00:00
idot4u.ll [AMDGPU] Fix typo in SIInstrInfo::memOpsHaveSameBasePtr 2019-12-17 18:54:27 +00:00
idot8s.ll [AMDGPU] Fix typo in SIInstrInfo::memOpsHaveSameBasePtr 2019-12-17 18:54:27 +00:00
idot8u.ll [codegen,amdgpu] Enhance MIR DIE and re-arrange it for AMDGPU. 2020-01-14 19:26:15 -05:00
illegal-sgpr-to-vgpr-copy.ll [AMDGPU] Fix illegal agpr use by VALU 2019-10-02 23:23:46 +00:00
image-attributes.ll
…
image-resource-id.ll
…
image-schedule.ll AMDGPU: Fix some outdated datalayouts in tests 2018-09-13 11:56:28 +00:00
image_ls_mipmap_zero.ll [AMDGPU] Optimize image_[load|store]_mip 2019-06-10 15:58:51 +00:00
img-nouse-adjust.ll [AMDGPU] Allow MIMG with no uses in adjustWritemask in isel 2019-03-20 09:29:55 +00:00
imm.ll [AMDGPU][MC][GFX8+][DISASSEMBLER] Corrected 1/2pi value for 64-bit operands 2019-01-18 15:17:17 +00:00
imm16.ll [DAGCombiner] allow narrowing of add followed by truncate 2018-12-22 17:10:31 +00:00
immv216.ll [AMDGPU] Preliminary patch for divergence driven instruction selection. Immediate selection predicate changed 2018-09-11 11:56:50 +00:00
implicit-def-muse.ll [AMDGPU] Come back patch for the 'Assign register class for cross block values according to the divergence.' 2019-10-14 12:01:10 +00:00
indirect-addressing-si-gfx9.ll [AMDGPU][MC][GFX8+] Added syntactic sugar for 'vgpr index' operand of instructions s_set_gpr_idx_on and s_set_gpr_idx_mode 2019-02-27 13:12:12 +00:00
indirect-addressing-si-noopt.ll [SDAG] fold extract_vector_elt with undef index 2019-10-25 19:27:26 -04:00
indirect-addressing-si-pregfx9.ll [AMDGPU][MC][GFX8+] Added syntactic sugar for 'vgpr index' operand of instructions s_set_gpr_idx_on and s_set_gpr_idx_mode 2019-02-27 13:12:12 +00:00
indirect-addressing-si.ll Revert [MBP] Disable aggressive loop rotate in plain mode 2019-08-29 19:03:58 +00:00
indirect-addressing-term.ll AMDGPU: Stop adding m0 implicit def to SGPR spills 2019-10-21 19:42:29 +00:00
indirect-private-64.ll
…
infer-addrpace-pipeline.ll
…
infinite-loop-evergreen.ll
…
infinite-loop.ll [MachineLICM][X86][AMDGPU] Fix subtle bug in the updating of PhysRegClobbers in post-RA LICM 2018-12-05 03:41:26 +00:00
inline-asm.ll AMDGPU: Make VReg_1 only include 1 artificial register 2019-10-28 20:51:51 -07:00
inline-attr.ll Add, and infer, a nofree function attribute 2019-07-08 15:57:56 +00:00
inline-calls.ll AMDGPU: Enable function calls by default 2019-02-28 00:40:32 +00:00
inline-constraints.ll AMDGPU: Relax 32-bit SGPR register class 2019-10-18 18:26:37 +00:00
inline-maxbb.ll [AMDGPU] Don't constrain callees with inlinehint from inlining on MaxBB check 2019-06-14 16:37:33 +00:00
inlineasm-16.ll
…
inlineasm-illegal-type.ll
…
inlineasm-packed.ll
…
input-mods.ll
…
insert-skip-from-vcc.mir [AMDGPU] gfx1010 core wave32 changes 2019-06-20 15:08:34 +00:00
insert-skips-flat-vmem.mir [AMDGPU] Invert the handling of skip insertion. 2020-01-15 15:18:16 +05:30
insert-skips-gws.mir [AMDGPU] Invert the handling of skip insertion. 2020-01-15 15:18:16 +05:30
insert-skips-ignored-insts.mir [AMDGPU] Invert the handling of skip insertion. 2020-01-15 15:18:16 +05:30
insert-skips-kill-uncond.mir [AMDGPU] Invert the handling of skip insertion. 2020-01-15 15:18:16 +05:30
insert-subvector-unused-scratch.ll [MachineScheduler] Reduce reordering due to mem op clustering 2020-01-14 19:19:02 +00:00
insert-waitcnts-callee.mir
…
insert-waitcnts-exp.mir [AMDGPU] Extend buffer intrinsics with swizzling 2019-10-02 17:22:36 +00:00
insert_subreg.ll
…
insert_vector_dynelt.ll [AMDGPU] Fix for vector element insertion 2019-02-01 16:51:09 +00:00
insert_vector_elt.ll [amdgpu] Fix typos in a test case. 2020-01-14 20:08:39 -05:00
insert_vector_elt.v2i16.ll [AMDGPU] Regenerate v2i16 insertelement tests. 2019-07-29 09:47:07 +00:00
insert_vector_elt.v2i16.subtest-nosaddr.ll [AMDGPU] Fix for vector element insertion 2019-02-01 16:51:09 +00:00
insert_vector_elt.v2i16.subtest-saddr.ll [AMDGPU] Fix for vector element insertion 2019-02-01 16:51:09 +00:00
inserted-wait-states.mir [AMDGPU] Fix-up cases where writelane has 2 SGPR operands 2019-10-16 14:37:39 +00:00
internalize.ll AMDGPU: Stop forcing internalize at -O0 2018-08-31 06:02:36 +00:00
invalid-addrspacecast.ll AMDGPU: Stop reporting is-noop addrspacecast for constant 32-bit 2018-09-10 11:59:27 +00:00
invalid-alloca.ll AMDGPU: Remove remnants of old address space mapping 2018-08-31 05:49:54 +00:00
invariant-load-no-alias-store.ll
…
invert-br-undef-vcc.mir [AMDGPU] Extend buffer intrinsics with swizzling 2019-10-02 17:22:36 +00:00
ipra-regmask.ll [AMDGPU] gfx908 register file changes 2019-07-09 19:41:51 +00:00
ipra.ll AMDGPU: Make s34 the FP register 2019-07-08 19:03:38 +00:00
jump-address.ll
…
kcache-fold.ll
…
kernarg-stack-alignment.ll
…
kernel-args.ll [MachineScheduler] Reduce reordering due to mem op clustering 2020-01-14 19:19:02 +00:00
kernel-argument-dag-lowering.ll [MachineScheduler] Reduce reordering due to mem op clustering 2020-01-14 19:19:02 +00:00
known-never-nan.ll DAG: Handle extract_vector_elt in isKnownNeverNaN 2018-09-03 14:01:03 +00:00
known-never-snan.ll AMDGPU: Always use s33 for global scratch wave offset 2019-06-20 21:58:24 +00:00
knownbits-recursion.ll
…
large-alloca-compute.ll [AMDGPU] gfx1010 tests. NFC. 2019-05-13 19:30:06 +00:00
large-alloca-graphics.ll
…
large-constant-initializer.ll AMDGPU: Fix tests using old number for constant address space 2018-09-10 02:54:25 +00:00
large-work-group-promote-alloca.ll AMDGPU Reduce reported maximum group size to 1024 2019-11-13 06:34:28 +05:30
lcssa-optnone.ll [AMDGPU] Run `unreachable-mbb-elimination` after isel to clean up PHIs. 2019-07-25 14:50:18 +00:00
lds-alignment.ll
…
lds-bounds.ll AMDGPU: Avoid selecting ds_{read,write}2_b32 on SI 2018-10-17 15:37:48 +00:00
lds-branch-vmem-hazard.mir [AMDGPU] Extend buffer intrinsics with swizzling 2019-10-02 17:22:36 +00:00
lds-global-non-entry-func.ll
…
lds-initializer.ll [Support] make report_fatal_error `abort` instead of `exit` 2020-01-15 17:05:13 -08:00
lds-m0-init-in-loop.ll
…
lds-misaligned-bug.ll [AMDGPU] gfx1011/gfx1012 targets 2019-06-14 00:33:31 +00:00
lds-oqap-crash.ll
…
lds-output-queue.ll
…
lds-relocs.ll AMDGPU: Write LDS objects out as global symbols in code generation 2019-06-25 11:52:30 +00:00
lds-size.ll AMDGPU: Write LDS objects out as global symbols in code generation 2019-06-25 11:52:30 +00:00
lds-zero-initializer.ll [Support] make report_fatal_error `abort` instead of `exit` 2020-01-15 17:05:13 -08:00
lds_atomic_f32.ll
…
legalize-fp-load-invariant.ll [AMDGPU] Rename pass "isel" to "amdgpu-isel" 2018-10-03 03:38:22 +00:00
legalizedag-bug-expand-setcc.ll
…
limit-coalesce.mir [Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing 2019-09-11 11:16:48 +00:00
lit.local.cfg
…
literals.ll
…
liveness.mir
…
llvm.amdgcn.alignb.ll
…
llvm.amdgcn.atomic.dec.ll AMDGPU: Write LDS objects out as global symbols in code generation 2019-06-25 11:52:30 +00:00
llvm.amdgcn.atomic.fadd.ll [AMDGPU] gfx908 atomic fadd and atomic pk_fadd 2019-07-11 00:10:17 +00:00
llvm.amdgcn.atomic.inc.ll [SelectionDAG] Propagate alias metadata to target intrinsic nodes 2019-07-03 14:33:29 +00:00
llvm.amdgcn.buffer.atomic.ll [AMDGPU] Add support for 64 bit buffer atomic artihmetic instructions 2019-03-06 17:02:06 +00:00
llvm.amdgcn.buffer.load.dwordx3.ll [AMDGPU] Implemented dwordx3 variants of buffer/tbuffer load/store intrinsics 2019-03-22 14:58:02 +00:00
llvm.amdgcn.buffer.load.format.d16.ll
…
llvm.amdgcn.buffer.load.format.ll
…
llvm.amdgcn.buffer.load.ll AMDGPU: Fold frame index into MUBUF 2019-06-24 14:53:56 +00:00
llvm.amdgcn.buffer.store.dwordx3.ll [AMDGPU] Implemented dwordx3 variants of buffer/tbuffer load/store intrinsics 2019-03-22 14:58:02 +00:00
llvm.amdgcn.buffer.store.format.d16.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
llvm.amdgcn.buffer.store.format.ll
…
llvm.amdgcn.buffer.store.ll [AMDGPU] Add buffer/load 8/16 bit overloaded intrinsics 2019-03-19 16:07:00 +00:00
llvm.amdgcn.buffer.wbinvl1.ll
…
llvm.amdgcn.buffer.wbinvl1.sc.ll
…
llvm.amdgcn.buffer.wbinvl1.vol.ll
…
llvm.amdgcn.class.f16.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
llvm.amdgcn.class.ll AMDGPU: Make s34 the FP register 2019-07-08 19:03:38 +00:00
llvm.amdgcn.cos.f16.ll
…
llvm.amdgcn.cos.ll
…
llvm.amdgcn.cubeid.ll
…
llvm.amdgcn.cubema.ll
…
llvm.amdgcn.cubesc.ll
…
llvm.amdgcn.cubetc.ll
…
llvm.amdgcn.cvt.pk.i16.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
llvm.amdgcn.cvt.pk.u16.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
llvm.amdgcn.cvt.pknorm.i16.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
llvm.amdgcn.cvt.pknorm.u16.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
llvm.amdgcn.cvt.pkrtz.ll [AMDGPU] Regenerate test file for upcoming patch. NFCI. 2019-07-19 15:43:56 +00:00
llvm.amdgcn.dispatch.id.ll
…
llvm.amdgcn.dispatch.ptr.ll AMDGPU: Enable code object v3 for AMDHSA only 2018-11-15 02:32:43 +00:00
llvm.amdgcn.div.fixup.f16.ll [AMDGPU] Preliminary patch for divergence driven instruction selection. Immediate selection predicate changed 2018-09-11 11:56:50 +00:00
llvm.amdgcn.div.fixup.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
llvm.amdgcn.div.fmas.ll AMDGPU: Rewrite SILowerI1Copies to always stay on SALU 2018-10-31 13:27:08 +00:00
llvm.amdgcn.div.scale.ll [AMDGPU] Come back patch for the 'Assign register class for cross block values according to the divergence.' 2019-10-14 12:01:10 +00:00
llvm.amdgcn.ds.append.ll AMDGPU: Fix dropping memref for ds append/consume 2019-06-14 21:01:24 +00:00
llvm.amdgcn.ds.bpermute.ll
…
llvm.amdgcn.ds.consume.ll AMDGPU: Fix dropping memref for ds append/consume 2019-06-14 21:01:24 +00:00
llvm.amdgcn.ds.gws.barrier.ll [AMDGPU] Fix bundle scheduling 2020-01-09 15:56:36 -08:00
llvm.amdgcn.ds.gws.init.ll [AMDGPU] Fix bundle scheduling 2020-01-09 15:56:36 -08:00
llvm.amdgcn.ds.gws.sema.br.ll AMDGPU: Don't rely on m0 being -1 for GWS offsets 2019-07-19 20:01:24 +00:00
llvm.amdgcn.ds.gws.sema.p.ll AMDGPU: Don't rely on m0 being -1 for GWS offsets 2019-07-19 20:01:24 +00:00
llvm.amdgcn.ds.gws.sema.release.all.ll [Support] make report_fatal_error `abort` instead of `exit` 2020-01-15 17:05:13 -08:00
llvm.amdgcn.ds.gws.sema.v.ll AMDGPU: Don't rely on m0 being -1 for GWS offsets 2019-07-19 20:01:24 +00:00
llvm.amdgcn.ds.ordered.add.gfx10.ll AMDGPU/GFX10: implement ds_ordered_count changes 2019-07-01 17:17:52 +00:00
llvm.amdgcn.ds.ordered.add.ll AMDGPU: Add llvm.amdgcn.ds.ordered.add & swap 2019-01-16 15:43:53 +00:00
llvm.amdgcn.ds.ordered.swap.ll [codegen,amdgpu] Enhance MIR DIE and re-arrange it for AMDGPU. 2020-01-14 19:26:15 -05:00
llvm.amdgcn.ds.permute.ll
…
llvm.amdgcn.ds.swizzle.ll
…
llvm.amdgcn.exp.compr.ll
…
llvm.amdgcn.exp.ll AMDGPU: Force skip over s_sendmsg and exp instructions 2018-07-30 09:23:59 +00:00
llvm.amdgcn.exp.prim.ll [AMDGPU] gfx1010 exp modifications 2019-05-08 21:23:37 +00:00
llvm.amdgcn.fcmp.ll IR: Add immarg attribute 2019-03-12 21:02:54 +00:00
llvm.amdgcn.fdiv.fast.ll
…
llvm.amdgcn.fdot2.ll [AMDGPU] gfx1011/gfx1012 targets 2019-06-14 00:33:31 +00:00
llvm.amdgcn.fmad.ftz.f16.ll [AMDGPU] Preliminary patch for divergence driven instruction selection. Immediate selection predicate changed 2018-09-11 11:56:50 +00:00
llvm.amdgcn.fmad.ftz.ll [AMDGPU] Preliminary patch for divergence driven instruction selection. Immediate selection predicate changed 2018-09-11 11:56:50 +00:00
llvm.amdgcn.fmed3.f16.ll
…
llvm.amdgcn.fmed3.ll [AMDGPU] Come back patch for the 'Assign register class for cross block values according to the divergence.' 2019-10-14 12:01:10 +00:00
llvm.amdgcn.fmul.legacy.ll
…
llvm.amdgcn.fract.f16.ll
…
llvm.amdgcn.fract.ll
…
llvm.amdgcn.frexp.exp.f16.ll
…
llvm.amdgcn.frexp.exp.ll
…
llvm.amdgcn.frexp.mant.f16.ll
…
llvm.amdgcn.frexp.mant.ll
…
llvm.amdgcn.groupstaticsize.ll AMDGPU: Write LDS objects out as global symbols in code generation 2019-06-25 11:52:30 +00:00
llvm.amdgcn.icmp.ll IR: Add immarg attribute 2019-03-12 21:02:54 +00:00
llvm.amdgcn.image.a16.dim.ll [AMDGPU] support image load/store a16 2018-10-31 10:34:48 +00:00
llvm.amdgcn.image.atomic.dim.ll [AMDGPU] gfx1010 MIMG implementation 2019-05-01 16:32:58 +00:00
llvm.amdgcn.image.d16.dim.ll [AMDGPU] gfx1010 MIMG implementation 2019-05-01 16:32:58 +00:00
llvm.amdgcn.image.dim.ll [AMDGPU] gfx1010 GCNNSAReassign pass 2019-05-01 16:40:49 +00:00
llvm.amdgcn.image.gather4.a16.dim.ll [AMDGPU] Add support for a16 modifiear for gfx9 2018-08-28 15:07:30 +00:00
llvm.amdgcn.image.gather4.d16.dim.ll [AMDGPU] gfx1010 MIMG implementation 2019-05-01 16:32:58 +00:00
llvm.amdgcn.image.gather4.dim.ll [AMDGPU] gfx1010 MIMG implementation 2019-05-01 16:32:58 +00:00
llvm.amdgcn.image.gather4.o.dim.ll AMDGPU: Convert test cases to the dimension-aware intrinsics 2018-06-21 13:37:19 +00:00
llvm.amdgcn.image.getlod.dim.ll [AMDGPU] gfx1010 MIMG implementation 2019-05-01 16:32:58 +00:00
llvm.amdgcn.image.load.a16.d16.ll [AMDGPU] Add support for TFE/LWE in image intrinsics. 2nd try 2019-01-14 11:55:24 +00:00
llvm.amdgcn.image.load.a16.ll [AMDGPU] Use three- and five-dword result type in image ops 2019-03-22 15:21:11 +00:00
llvm.amdgcn.image.nsa.ll [AMDGPU] gfx1010 MIMG implementation 2019-05-01 16:32:58 +00:00
llvm.amdgcn.image.sample.a16.dim.ll [AMDGPU] Add support for a16 modifiear for gfx9 2018-08-28 15:07:30 +00:00
llvm.amdgcn.image.sample.d16.dim.ll [AMDGPU] gfx1010 MIMG implementation 2019-05-01 16:32:58 +00:00
llvm.amdgcn.image.sample.dim.ll [AMDGPU] gfx1010 MIMG implementation 2019-05-01 16:32:58 +00:00
llvm.amdgcn.image.sample.ltolz.ll [AMDGPU] Optimize _L image intrinsic to _LZ when lod is zero 2018-08-01 12:12:01 +00:00
llvm.amdgcn.image.sample.o.dim.ll AMDGPU: Convert test cases to the dimension-aware intrinsics 2018-06-21 13:37:19 +00:00
llvm.amdgcn.image.store.a16.d16.ll [AMDGPU] support image load/store a16 2018-10-31 10:34:48 +00:00
llvm.amdgcn.image.store.a16.ll [AMDGPU] support image load/store a16 2018-10-31 10:34:48 +00:00
llvm.amdgcn.implicit.buffer.ptr.hsa.ll
…
llvm.amdgcn.implicit.buffer.ptr.ll AMDGPU: Revert accidental change to test 2019-07-01 19:09:57 +00:00
llvm.amdgcn.implicitarg.ptr.ll AMDGPU: Make s34 the FP register 2019-07-08 19:03:38 +00:00
llvm.amdgcn.init.exec.ll AMDGPU/GlobalISel: Add support for init.exec intrinsics 2019-10-01 02:07:25 +00:00
llvm.amdgcn.init.exec.wave32.ll AMDGPU/GlobalISel: Add support for init.exec intrinsics 2019-10-01 02:07:25 +00:00
llvm.amdgcn.interp.f16.ll AMDGPU: Use CopyToReg for interp intrinsic lowering 2019-10-21 19:53:49 +00:00
llvm.amdgcn.interp.ll AMDGPU: Drop remnants of byval support for shaders 2019-07-12 20:12:17 +00:00
llvm.amdgcn.is.private.ll AMDGPU: Add intrinsics for address space identification 2019-09-05 02:20:39 +00:00
llvm.amdgcn.is.shared.ll AMDGPU: Add intrinsics for address space identification 2019-09-05 02:20:39 +00:00
llvm.amdgcn.kernarg.segment.ptr.ll AMDGPU: Enable code object v3 for AMDHSA only 2018-11-15 02:32:43 +00:00
llvm.amdgcn.kill.ll [AMDGPU] more gfx1010 tests. NFC. 2019-06-12 18:44:11 +00:00
llvm.amdgcn.ldexp.f16.ll
…
llvm.amdgcn.ldexp.ll
…
llvm.amdgcn.lerp.ll [AMDGPU] Preliminary patch for divergence driven instruction selection. Immediate selection predicate changed 2018-09-11 11:56:50 +00:00
llvm.amdgcn.log.clamp.ll
…
llvm.amdgcn.mbcnt.ll AMDGPU: Fix tests using old number for constant address space 2018-09-10 02:54:25 +00:00
llvm.amdgcn.mfma.ll AMDGPU: Fix lit test checks with dag option 2019-11-28 10:01:06 +00:00
llvm.amdgcn.mov.dpp.ll [AMDGPU] Fixed dpp test. NFC. 2019-11-13 16:38:54 -08:00
llvm.amdgcn.mov.dpp8.ll [AMDGPU] gfx1010 dpp16 and dpp8 2019-06-12 18:02:41 +00:00
llvm.amdgcn.mqsad.pk.u16.u8.ll [AMDGPU] Come back patch for the 'Assign register class for cross block values according to the divergence.' 2019-10-14 12:01:10 +00:00
llvm.amdgcn.mqsad.u32.u8.ll
…
llvm.amdgcn.msad.u8.ll [AMDGPU] Preliminary patch for divergence driven instruction selection. Immediate selection predicate changed 2018-09-11 11:56:50 +00:00
llvm.amdgcn.mul.i24.ll AMDGPU: Add 24-bit mul intrinsics 2019-07-15 17:50:31 +00:00
llvm.amdgcn.mul.u24.ll AMDGPU: Add 24-bit mul intrinsics 2019-07-15 17:50:31 +00:00
llvm.amdgcn.permlane.ll [AMDGPU] gfx1010 premlane instructions 2019-06-12 17:52:51 +00:00
llvm.amdgcn.ps.live.ll AMDGPU: Convert test cases to the dimension-aware intrinsics 2018-06-21 13:37:19 +00:00
llvm.amdgcn.qsad.pk.u16.u8.ll [AMDGPU] Come back patch for the 'Assign register class for cross block values according to the divergence.' 2019-10-14 12:01:10 +00:00
llvm.amdgcn.queue.ptr.ll AMDGPU: Enable code object v3 for AMDHSA only 2018-11-15 02:32:43 +00:00
llvm.amdgcn.raw.buffer.atomic.ll AMDGPU: add missing llvm.amdgcn.{raw,struct}.buffer.atomic.{inc,dec} 2019-08-05 09:36:06 +00:00
llvm.amdgcn.raw.buffer.load.format.d16.ll [AMDGPU] New buffer intrinsics 2018-08-21 11:07:10 +00:00
llvm.amdgcn.raw.buffer.load.format.ll [AMDGPU] New buffer intrinsics 2018-08-21 11:07:10 +00:00
llvm.amdgcn.raw.buffer.load.ll [AMDGPU] Extend buffer intrinsics with swizzling 2019-10-02 17:22:36 +00:00
llvm.amdgcn.raw.buffer.store.format.d16.ll [AMDGPU] New buffer intrinsics 2018-08-21 11:07:10 +00:00
llvm.amdgcn.raw.buffer.store.format.ll [AMDGPU] New buffer intrinsics 2018-08-21 11:07:10 +00:00
llvm.amdgcn.raw.buffer.store.ll [AMDGPU] Extend buffer intrinsics with swizzling 2019-10-02 17:22:36 +00:00
llvm.amdgcn.raw.tbuffer.load.d16.ll [AMDGPU] gfx1010 MIMG implementation 2019-05-01 16:32:58 +00:00
llvm.amdgcn.raw.tbuffer.load.ll [AMDGPU] gfx1010 tests. NFC. 2019-05-08 23:31:32 +00:00
llvm.amdgcn.raw.tbuffer.store.d16.ll [AMDGPU] gfx1010 MIMG implementation 2019-05-01 16:32:58 +00:00
llvm.amdgcn.raw.tbuffer.store.ll [AMDGPU] gfx1010 MIMG implementation 2019-05-01 16:32:58 +00:00
llvm.amdgcn.rcp.f16.ll
…
llvm.amdgcn.rcp.legacy.ll
…
llvm.amdgcn.rcp.ll
…
llvm.amdgcn.readfirstlane.ll AMDGPU: Relax 32-bit SGPR register class 2019-10-18 18:26:37 +00:00
llvm.amdgcn.readlane.ll AMDGPU: Relax 32-bit SGPR register class 2019-10-18 18:26:37 +00:00
llvm.amdgcn.rsq.clamp.ll
…
llvm.amdgcn.rsq.f16.ll
…
llvm.amdgcn.rsq.legacy.ll
…
llvm.amdgcn.rsq.ll
…
llvm.amdgcn.s.barrier.ll [AMDGPU] Mark s_barrier as having side effects but not accessing memory. 2019-09-06 10:07:28 +00:00
llvm.amdgcn.s.buffer.load.ll [AMDGPU] Lower llvm.amdgcn.s.buffer.load.v3[i|f]32 2019-11-15 15:01:15 +01:00
llvm.amdgcn.s.dcache.inv.ll
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llvm.amdgcn.s.dcache.inv.vol.ll
…
llvm.amdgcn.s.dcache.wb.ll
…
llvm.amdgcn.s.dcache.wb.vol.ll
…
llvm.amdgcn.s.decperflevel.ll
…
llvm.amdgcn.s.get.waveid.in.workgroup.ll [AMDGPU] gfx1010 VMEM and SMEM implementation 2019-04-30 22:08:23 +00:00
llvm.amdgcn.s.getpc.ll
…
llvm.amdgcn.s.getreg.ll
…
llvm.amdgcn.s.incperflevel.ll
…
llvm.amdgcn.s.memrealtime.ll
…
llvm.amdgcn.s.memtime.ll
…
llvm.amdgcn.s.sleep.ll
…
llvm.amdgcn.s.waitcnt.ll AMDGPU: s_waitcnt field should be treated as unsigned 2019-07-11 23:42:57 +00:00
llvm.amdgcn.sad.hi.u8.ll [AMDGPU] Preliminary patch for divergence driven instruction selection. Immediate selection predicate changed 2018-09-11 11:56:50 +00:00
llvm.amdgcn.sad.u8.ll [AMDGPU] Preliminary patch for divergence driven instruction selection. Immediate selection predicate changed 2018-09-11 11:56:50 +00:00
llvm.amdgcn.sad.u16.ll [AMDGPU] Preliminary patch for divergence driven instruction selection. Immediate selection predicate changed 2018-09-11 11:56:50 +00:00
llvm.amdgcn.sbfe.ll
…
llvm.amdgcn.sdot2.ll [AMDGPU] gfx908 dot instruction support 2019-07-11 00:00:27 +00:00
llvm.amdgcn.sdot4.ll [AMDGPU] gfx1011/gfx1012 targets 2019-06-14 00:33:31 +00:00
llvm.amdgcn.sdot8.ll [AMDGPU] gfx908 dot instruction support 2019-07-11 00:00:27 +00:00
llvm.amdgcn.sendmsg.ll [AMDGPU][MC] Enabled constant expressions as operands of sendmsg 2019-06-28 14:14:02 +00:00
llvm.amdgcn.set.inactive.ll
…
llvm.amdgcn.sffbh.ll
…
llvm.amdgcn.sin.f16.ll
…
llvm.amdgcn.sin.ll
…
llvm.amdgcn.softwqm.ll [AMDGPU] Add llvm.amdgcn.softwqm intrinsic 2019-07-26 09:54:12 +00:00
llvm.amdgcn.struct.buffer.atomic.ll AMDGPU: add missing llvm.amdgcn.{raw,struct}.buffer.atomic.{inc,dec} 2019-08-05 09:36:06 +00:00
llvm.amdgcn.struct.buffer.load.format.d16.ll [AMDGPU] New buffer intrinsics 2018-08-21 11:07:10 +00:00
llvm.amdgcn.struct.buffer.load.format.ll [AMDGPU] New buffer intrinsics 2018-08-21 11:07:10 +00:00
llvm.amdgcn.struct.buffer.load.ll AMDGPU: Correct behavior of f16 buffer loads 2019-08-05 15:59:07 +00:00
llvm.amdgcn.struct.buffer.store.format.d16.ll [AMDGPU] New buffer intrinsics 2018-08-21 11:07:10 +00:00
llvm.amdgcn.struct.buffer.store.format.ll [AMDGPU] New buffer intrinsics 2018-08-21 11:07:10 +00:00
llvm.amdgcn.struct.buffer.store.ll AMDGPU: Correct behavior of f16/i16 non-format store intrinsics 2019-08-05 14:57:59 +00:00
llvm.amdgcn.struct.tbuffer.load.d16.ll [AMDGPU] gfx1010 MIMG implementation 2019-05-01 16:32:58 +00:00
llvm.amdgcn.struct.tbuffer.load.ll [AMDGPU] gfx1010 MIMG implementation 2019-05-01 16:32:58 +00:00
llvm.amdgcn.struct.tbuffer.store.d16.ll [AMDGPU] gfx1010 MIMG implementation 2019-05-01 16:32:58 +00:00
llvm.amdgcn.struct.tbuffer.store.ll [AMDGPU] gfx1010 MIMG implementation 2019-05-01 16:32:58 +00:00
llvm.amdgcn.tbuffer.load.d16.ll
…
llvm.amdgcn.tbuffer.load.dwordx3.ll [AMDGPU] Implemented dwordx3 variants of buffer/tbuffer load/store intrinsics 2019-03-22 14:58:02 +00:00
llvm.amdgcn.tbuffer.load.ll
…
llvm.amdgcn.tbuffer.store.d16.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
llvm.amdgcn.tbuffer.store.dwordx3.ll [AMDGPU] Implemented dwordx3 variants of buffer/tbuffer load/store intrinsics 2019-03-22 14:58:02 +00:00
llvm.amdgcn.tbuffer.store.ll [AMDGPU] New tbuffer intrinsics 2018-08-21 11:06:05 +00:00
llvm.amdgcn.trig.preop.ll
…
llvm.amdgcn.ubfe.ll UpdateTestChecks: fix AMDGPU handling 2019-05-18 13:00:03 +00:00
llvm.amdgcn.udot2.ll [AMDGPU] gfx1011/gfx1012 targets 2019-06-14 00:33:31 +00:00
llvm.amdgcn.udot4.ll [AMDGPU] gfx1011/gfx1012 targets 2019-06-14 00:33:31 +00:00
llvm.amdgcn.udot8.ll [AMDGPU] gfx1011/gfx1012 targets 2019-06-14 00:33:31 +00:00
llvm.amdgcn.unreachable.ll
…
llvm.amdgcn.update.dpp.ll [AMDGPU] Support mov dpp with 64 bit operands 2019-10-15 16:41:15 +00:00
llvm.amdgcn.wave.barrier.ll AMDGPU: wave_barrier is not isBarrier 2019-03-27 15:54:45 +00:00
llvm.amdgcn.wavefrontsize.ll [AMDGPU] gfx1010 wavefrontsize intrinsic folding 2019-06-17 17:57:50 +00:00
llvm.amdgcn.workgroup.id.ll AMDGPU: Enable code object v3 for AMDHSA only 2018-11-15 02:32:43 +00:00
llvm.amdgcn.workitem.id.ll AMDGPU: Enable code object v3 for AMDHSA only 2018-11-15 02:32:43 +00:00
llvm.amdgcn.wqm.vote.ll AMDGPU/GlobalISel: Select llvm.amdgcn.wqm.vote 2020-01-07 10:15:29 -05:00
llvm.amdgcn.writelane.ll AMDGPU: Relax 32-bit SGPR register class 2019-10-18 18:26:37 +00:00
llvm.ceil.f16.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
llvm.cos.f16.ll [AMDGPU] Ensure trig range reduction only used for subtargets that require it 2018-09-14 10:27:19 +00:00
llvm.cos.ll
…
llvm.dbg.value.ll [DebugInfo] Stop changing labels for register-described parameter DBG_VALUEs 2019-02-13 09:34:07 +00:00
llvm.exp2.f16.ll
…
llvm.exp2.ll [FileCheck] Add -allow-deprecated-dag-overlap to failing llvm tests 2018-07-11 20:25:49 +00:00
llvm.floor.f16.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
llvm.fma.f16.ll [AMDGPU] Enable v4f16 and above for v_pk_fma instructions 2019-07-29 08:15:10 +00:00
llvm.fmuladd.f16.ll [AMDGPU] gfx1010: use fmac instructions 2019-05-04 04:20:37 +00:00
llvm.log.f16.ll [AMDGPU] Created a sub-register class for the return address operand in the return instruction. 2019-07-09 16:48:42 +00:00
llvm.log.ll [AMDGPU] Preliminary patch for divergence driven instruction selection. Immediate selection predicate changed 2018-09-11 11:56:50 +00:00
llvm.log2.f16.ll
…
llvm.log2.ll [FileCheck] Add -allow-deprecated-dag-overlap to failing llvm tests 2018-07-11 20:25:49 +00:00
llvm.log10.f16.ll [AMDGPU] Created a sub-register class for the return address operand in the return instruction. 2019-07-09 16:48:42 +00:00
llvm.log10.ll [AMDGPU] Preliminary patch for divergence driven instruction selection. Immediate selection predicate changed 2018-09-11 11:56:50 +00:00
llvm.maxnum.f16.ll [AMDGPU] Fix typo in SIInstrInfo::memOpsHaveSameBasePtr 2019-12-17 18:54:27 +00:00
llvm.memcpy.ll AMDGPU: Be explicit about whether the high-word in SI_PC_ADD_REL_OFFSET is 0 2019-06-16 17:32:01 +00:00
llvm.minnum.f16.ll [AMDGPU] Fix typo in SIInstrInfo::memOpsHaveSameBasePtr 2019-12-17 18:54:27 +00:00
llvm.pow.ll
…
llvm.r600.cube.ll
…
llvm.r600.dot4.ll
…
llvm.r600.group.barrier.ll
…
llvm.r600.read.local.size.ll
…
llvm.r600.recipsqrt.clamped.ll
…
llvm.r600.recipsqrt.ieee.ll
…
llvm.r600.tex.ll
…
llvm.rint.f16.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
llvm.rint.f64.ll
…
llvm.rint.ll
…
llvm.round.f64.ll [codegen,amdgpu] Enhance MIR DIE and re-arrange it for AMDGPU. 2020-01-14 19:26:15 -05:00
llvm.round.ll
…
llvm.sin.f16.ll [AMDGPU] Ensure trig range reduction only used for subtargets that require it 2018-09-14 10:27:19 +00:00
llvm.sin.ll [AMDGPU] Ensure trig range reduction only used for subtargets that require it 2018-09-14 10:27:19 +00:00
llvm.sqrt.f16.ll
…
llvm.trunc.f16.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
load-constant-f32.ll
…
load-constant-f64.ll
…
load-constant-i1.ll AMDGPU: Remove remnants of old address space mapping 2018-08-31 05:49:54 +00:00
load-constant-i8.ll [FileCheck] Add -allow-deprecated-dag-overlap to failing llvm tests 2018-07-11 20:25:49 +00:00
load-constant-i16.ll [LegalizeVectorTypes] Allow single loads and stores for more short vectors 2019-03-27 20:35:56 +00:00
load-constant-i32.ll [AMDGPU] gfx908 mfma support 2019-07-11 21:19:33 +00:00
load-constant-i64.ll
…
load-global-f32.ll [AMDGPU] Support for v3i32/v3f32 2019-03-21 12:01:21 +00:00
load-global-f64.ll
…
load-global-i1.ll AMDGPU: Remove remnants of old address space mapping 2018-08-31 05:49:54 +00:00
load-global-i8.ll [FileCheck] Add -allow-deprecated-dag-overlap to failing llvm tests 2018-07-11 20:25:49 +00:00
load-global-i16.ll [LegalizeVectorTypes] Allow single loads and stores for more short vectors 2019-03-27 20:35:56 +00:00
load-global-i32.ll [AMDGPU] gfx908 mfma support 2019-07-11 21:19:33 +00:00
load-global-i64.ll
…
load-hi16.ll AMDGPU: Always use s33 for global scratch wave offset 2019-06-20 21:58:24 +00:00
load-input-fold.ll
…
load-lo16.ll [AMDGPU] Clean up update_llc_test_checks CodeGen tests 2019-10-24 17:35:33 -04:00
load-local-f32-no-ds128.ll
…
load-local-f32.ll
…
load-local-f64.ll
…
load-local-i1.ll AMDGPU: Remove remnants of old address space mapping 2018-08-31 05:49:54 +00:00
load-local-i8.ll AMDGPU: Remove remnants of old address space mapping 2018-08-31 05:49:54 +00:00
load-local-i16.ll [LegalizeVectorTypes] Allow single loads and stores for more short vectors 2019-03-27 20:35:56 +00:00
load-local-i32.ll [AMDGPU] gfx908 mfma support 2019-07-11 21:19:33 +00:00
load-local-i64.ll
…
load-select-ptr.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
load-weird-sizes.ll
…
local-64.ll [AMDGPU] Shrink scalar AND, OR, XOR instructions 2018-12-07 15:33:21 +00:00
local-atomics-fp.ll AMDGPU: Add support for cross address space synchronization scopes 2019-03-25 20:50:21 +00:00
local-atomics.ll Allow FP types for atomicrmw xchg 2019-01-17 10:49:01 +00:00
local-atomics64.ll Allow FP types for atomicrmw xchg 2019-01-17 10:49:01 +00:00
local-memory.amdgcn.ll [AMDGPU] Mark s_barrier as having side effects but not accessing memory. 2019-09-06 10:07:28 +00:00
local-memory.ll AMDGPU: Write LDS objects out as global symbols in code generation 2019-06-25 11:52:30 +00:00
local-memory.r600.ll
…
local-stack-slot-offset.ll [AMDGPU] Remove FeatureVGPRSpilling 2018-10-31 18:54:06 +00:00
loop-address.ll
…
loop-idiom.ll AMDGPU: Fix tests using the default alloca address space 2019-07-01 15:23:03 +00:00
loop_break.ll [codegen,amdgpu] Enhance MIR DIE and re-arrange it for AMDGPU. 2020-01-14 19:26:15 -05:00
loop_exit_with_xor.ll Revert [MBP] Disable aggressive loop rotate in plain mode 2019-08-29 19:03:58 +00:00
loop_header_nopred.mir [MBP] Avoid tail duplication if it can't bring benefit 2019-12-06 09:53:53 -08:00
lower-kernargs.ll AMDGPU: Partially fix default device for HSA 2019-03-17 21:31:35 +00:00
lower-mem-intrinsics.ll
…
lower-range-metadata-intrinsic-call.ll AMDGPU: Switch backend default max workgroup size to 1024 2019-11-13 07:11:02 +05:30
lshl64-to-32.ll AMDGPU: Don't use the default cpu in a few tests 2019-04-03 00:00:58 +00:00
lshr.v2i16.ll [SelectionDAG] ComputeKnownBits - minimum leading/trailing zero bits in LSHR/SHL (PR44526) 2020-01-13 11:08:12 +00:00
macro-fusion-cluster-vcc-uses.mir [AMDGPU] Asm/disasm clamp modifier on vop3 int arithmetic 2019-03-18 19:35:44 +00:00
mad-combine.ll
…
mad-mix-hi.ll AMDGPU: Remove custom BUILD_VECTOR combine 2018-10-30 01:37:59 +00:00
mad-mix-lo.ll [AMDGPU] Support for v3i32/v3f32 2019-03-21 12:01:21 +00:00
mad-mix.ll [AMDGPU] Preliminary patch for divergence driven instruction selection. Immediate selection predicate changed 2018-09-11 11:56:50 +00:00
mad.u16.ll [AMDGPU] gfx1010 lost VOP2 forms of some add/sub 2019-05-02 04:26:35 +00:00
mad24-get-global-id.ll
…
mad_64_32.ll AMDGPU: Make s34 the FP register 2019-07-08 19:03:38 +00:00
mad_int24.ll AMDGPU: Combine directly on mul24 intrinsics 2019-08-27 00:18:09 +00:00
mad_uint24.ll AMDGPU: Add 24-bit mul intrinsics 2019-07-15 17:50:31 +00:00
madak-inline-constant.mir [AMDGPU] Preliminary patch for divergence driven instruction selection. Inline immediate move to V_MADAK_F32. 2018-09-10 16:42:49 +00:00
madak.ll [AMDGPU] Fix typo in SIInstrInfo::memOpsHaveSameBasePtr 2019-12-17 18:54:27 +00:00
madmk.ll [MBP] Move a latch block with conditional exit and multi predecessors to top of loop 2019-06-14 23:08:59 +00:00
mai-hazards.mir [AMDGPU] gfx908 hazard recognizer 2019-07-11 21:30:34 +00:00
mai-inline.ll [AMDGPU] gfx908 mfma support 2019-07-11 21:19:33 +00:00
max-literals.ll
…
max-sgprs.ll [AMDGPU] gfx1010 VOP2 changes 2019-04-26 16:37:51 +00:00
max.i16.ll [MachineScheduler] Reduce reordering due to mem op clustering 2020-01-14 19:19:02 +00:00
max.ll [AMDGPU] Unnecessary -amdgpu-scalarize-global-loads=false flag removed from min/max lit tests. 2019-09-19 16:44:38 +00:00
max3.ll [AMDGPU] Ban i8 min3 promotion. 2019-03-19 15:50:24 +00:00
mcp-overlap-after-propagation.mir MCP: Fixed bug with dest overlapping copy source 2019-11-12 08:18:11 +00:00
med3-no-simplify.ll Reapply [ValueTracking] Support min/max selects in computeConstantRange() 2019-04-07 17:22:16 +00:00
mem-builtins.ll [AMDGPU] Mark test functions with hidden visibility 2019-02-01 21:23:28 +00:00
memory-legalizer-amdpal.ll AMDGPU: Add support for cross address space synchronization scopes 2019-03-25 20:50:21 +00:00
memory-legalizer-atomic-cmpxchg.ll [AMDGPU] gfx1010 memory legalizer 2019-05-06 21:57:02 +00:00
memory-legalizer-atomic-fence.ll [AMDGPU] gfx1010 memory legalizer 2019-05-06 21:57:02 +00:00
memory-legalizer-atomic-insert-end.mir llc: Change behavior of -mcpu with existing attribute 2020-01-07 10:10:25 -05:00
memory-legalizer-atomic-rmw.ll [AMDGPU] gfx1010 memory legalizer 2019-05-06 21:57:02 +00:00
memory-legalizer-invalid-addrspace.mir [AMDGPU] gfx1010 VMEM and SMEM implementation 2019-04-30 22:08:23 +00:00
memory-legalizer-invalid-syncscope.ll [AMDGPU] gfx1010 memory legalizer 2019-05-06 21:57:02 +00:00
memory-legalizer-load.ll [AMDGPU] gfx1010 memory legalizer 2019-05-06 21:57:02 +00:00
memory-legalizer-local.mir [AMDGPU] gfx1010 VMEM and SMEM implementation 2019-04-30 22:08:23 +00:00
memory-legalizer-mesa3d.ll AMDGPU: Add support for cross address space synchronization scopes 2019-03-25 20:50:21 +00:00
memory-legalizer-multiple-mem-operands-atomics.mir [AMDGPU] Extend buffer intrinsics with swizzling 2019-10-02 17:22:36 +00:00
memory-legalizer-multiple-mem-operands-nontemporal-1.mir [AMDGPU] Extend buffer intrinsics with swizzling 2019-10-02 17:22:36 +00:00
memory-legalizer-multiple-mem-operands-nontemporal-2.mir [AMDGPU] Extend buffer intrinsics with swizzling 2019-10-02 17:22:36 +00:00
memory-legalizer-region.mir [AMDGPU] gfx1010 VMEM and SMEM implementation 2019-04-30 22:08:23 +00:00
memory-legalizer-store-infinite-loop.ll AMDGPU: Remove remnants of old address space mapping 2018-08-31 05:49:54 +00:00
memory-legalizer-store.ll [AMDGPU] gfx1010 memory legalizer 2019-05-06 21:57:02 +00:00
memory_clause.ll [AMDGPU] Automatically generate various tests. NFC 2019-08-23 17:58:49 +00:00
memory_clause.mir AMDGPU: Use SGPR_128 instead of SReg_128 for vregs 2019-10-10 07:11:33 +00:00
merge-image-load.mir [AMDGPU] Extend the SI Load/Store optimizer 2019-10-16 10:17:02 +00:00
merge-image-sample.mir [AMDGPU] Extend the SI Load/Store optimizer 2019-10-16 10:17:02 +00:00
merge-load-store-physreg.mir AMDGPU: Remove unnecessary IR from test 2019-10-14 18:30:29 +00:00
merge-load-store-vreg.mir [AMDGPU] Asm/disasm v_cndmask_b32_e64 with abs/neg source modifiers 2019-03-18 19:25:39 +00:00
merge-load-store.mir AMDGPU: Use SGPR_128 instead of SReg_128 for vregs 2019-10-10 07:11:33 +00:00
merge-m0.mir AMDGPU: Move m0 initializations earlier 2019-09-11 21:28:41 +00:00
merge-store-crash.ll AMDGPU: Write LDS objects out as global symbols in code generation 2019-06-25 11:52:30 +00:00
merge-store-usedef.ll
…
merge-stores.ll [AMDGPU] Support for v3i32/v3f32 2019-03-21 12:01:21 +00:00
merge-tbuffer.mir [AMDGPU][SILoadStoreOptimizer] Merge TBUFFER loads/stores 2019-11-20 22:59:30 +01:00
mesa3d.ll AMDGPU: Fix not adding ImplicitBufferPtr as a live-in 2019-05-31 22:47:36 +00:00
mesa_regression.ll
…
mfma-loop.ll [AMDGPU] Fixed mfma-loop test. NFC. 2019-11-13 16:03:54 -08:00
min.ll [AMDGPU] Fix bundle scheduling 2020-01-09 15:56:36 -08:00
min3.ll [AMDGPU] Ban i8 min3 promotion. 2019-03-19 15:50:24 +00:00
mir-print-dead-csr-fi.mir MIR: Fix printer crashing on dead CSR frame indexes 2019-05-28 13:08:31 +00:00
misched-killflags.mir [AMDGPU] Fix bundle scheduling 2020-01-09 15:56:36 -08:00
missing-store.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
mixed-wave32-wave64.ll [AMDGPU] gfx10 tests. NFC. 2019-06-20 16:29:40 +00:00
mixed_wave32_wave64.ll [AMDGPU] gfx10 tests. NFC. 2019-06-20 16:29:40 +00:00
mode-register.mir [AMDGPU] Add support for immediate operand for S_ENDPGM 2019-03-12 09:52:58 +00:00
move-addr64-rsrc-dead-subreg-writes.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
move-to-valu-atomicrmw.ll
…
move-to-valu-worklist.ll
…
movreld-bug.ll AMDGPU: Add gfx9 run lines to a testcase 2020-01-03 15:25:50 -05:00
movrels-bug.mir [AMDGPU] Add support for immediate operand for S_ENDPGM 2019-03-12 09:52:58 +00:00
mubuf-legalize-operands.ll [AMDGPU] Invert the handling of skip insertion. 2020-01-15 15:18:16 +05:30
mubuf-legalize-operands.mir AMDGPU: Use SGPR_128 instead of SReg_128 for vregs 2019-10-10 07:11:33 +00:00
mubuf-offset-private.ll
…
mubuf-shader-vgpr.ll
…
mubuf.ll AMDGPU: Drop remnants of byval support for shaders 2019-07-12 20:12:17 +00:00
mul.i16.ll AMDGPU: Add 24-bit mul intrinsics 2019-07-15 17:50:31 +00:00
mul.ll AMDGPU: Temporary drop s_mul_hi_i/u32 patterns 2019-05-28 21:18:34 +00:00
mul24-pass-ordering.ll [AMDGPU] Invert the handling of skip insertion. 2020-01-15 15:18:16 +05:30
mul_int24.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
mul_uint24-amdgcn.ll [AMDGPU] Fix bundle scheduling 2020-01-09 15:56:36 -08:00
mul_uint24-r600.ll
…
multi-divergent-exit-region.ll [AMDGPU] gfx1010 wave32 icmp/fcmp intrinsic changes for wave32 2019-06-13 23:47:36 +00:00
multi-dword-vgpr-spill.ll AMDGPU: Don't fix emergency stack slot at offset 0 2019-06-05 22:37:50 +00:00
multilevel-break.ll [AMDGPU] Fix emitIfBreak CF lowering: use temp reg to make register coalescer life easier. 2019-11-26 18:59:37 +03:00
nand.ll [AMDGPU] Add and update scalar instructions 2018-11-29 16:05:38 +00:00
nested-calls.ll [AMDGPU] Created a sub-register class for the return address operand in the return instruction. 2019-07-09 16:48:42 +00:00
nested-loop-conditions.ll [AMDGPU] gfx1010 wave32 icmp/fcmp intrinsic changes for wave32 2019-06-13 23:47:36 +00:00
no-hsa-graphics-shaders.ll
…
no-initializer-constant-addrspace.ll Use -mtriple to fix AMDGPU test sensitive to object file format 2019-09-05 00:34:01 +00:00
no-remat-indirect-mov.mir AMDGPU: Don't rematerialize mov with implicit operands 2019-02-04 22:26:21 +00:00
no-shrink-extloads.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
noop-shader-O0.ll [AMDGPU] Remove FeatureVGPRSpilling 2018-10-31 18:54:06 +00:00
nop-data.ll [llvm-objdump] Tidy up AMDGCNPrettyPrinter 2019-06-18 06:35:18 +00:00
nop-fold.mir AMDGPU: Don't fold S_NOPs with implicit operands 2019-10-30 14:40:56 -07:00
nor.ll [AMDGPU] Add and update scalar instructions 2018-11-29 16:05:38 +00:00
not-scalarize-volatile-load.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
nsa-reassign.ll [AMDGPU] Fix high occupancy calculation and print it 2019-07-31 01:07:10 +00:00
nsa-vmem-hazard.mir [AMDGPU] Extend buffer intrinsics with swizzling 2019-10-02 17:22:36 +00:00
nullptr.ll AMDGPU: Remove remnants of old address space mapping 2018-08-31 05:49:54 +00:00
occupancy-levels.ll AMDGPU: Switch backend default max workgroup size to 1024 2019-11-13 07:11:02 +05:30
offset-split-flat.ll AMDGPU: Split flat offsets that don't fit in DAG 2019-10-20 17:34:44 +00:00
offset-split-global.ll AMDGPU: Split flat offsets that don't fit in DAG 2019-10-20 17:34:44 +00:00
omod-nsz-flag.mir AMDGPU: Be explicit about denormal mode in MIR tests 2019-11-19 19:55:43 +05:30
omod.ll
…
opencl-image-metadata.ll
…
opencl-printf-no-hostcall.ll [AMDGPU] add support for hostcall buffer pointer as hidden kernel argument 2019-11-20 15:53:55 +05:30
opencl-printf.ll [AMDGPU] Printf runtime binding pass 2019-08-12 17:12:29 +00:00
operand-folding.ll [AMDGPU] Skip additional folding on the same operand. 2019-10-24 11:30:22 -04:00
operand-spacing.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
opt-sgpr-to-vgpr-copy.mir [AMDGPU] Extend buffer intrinsics with swizzling 2019-10-02 17:22:36 +00:00
optimize-exec-masking-pre-ra.mir AMDGPU: Propagate undef flag during pre-RA exec mask optimizations 2019-10-08 12:46:32 +00:00
optimize-if-exec-masking.mir [AMDGPU] Extend buffer intrinsics with swizzling 2019-10-02 17:22:36 +00:00
optimize-negated-cond-exec-masking-wave32.mir [AMDGPU] gfx10 tests. NFC. 2019-06-20 16:29:40 +00:00
optimize-negated-cond-exec-masking.mir AMDGPU: Use SGPR_128 instead of SReg_128 for vregs 2019-10-10 07:11:33 +00:00
optimize-negated-cond.ll Revert [MBP] Disable aggressive loop rotate in plain mode 2019-08-29 19:03:58 +00:00
or.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
or3.ll [AMDGPU] gfx1010 core wave32 changes 2019-06-20 15:08:34 +00:00
pack.v2f16.ll
…
pack.v2i16.ll
…
packed-op-sel.ll [AMDGPU] Fix bundle scheduling 2020-01-09 15:56:36 -08:00
packetizer.ll
…
parallelandifcollapse.ll
…
parallelorifcollapse.ll
…
partial-sgpr-to-vgpr-spills.ll RegAllocFast: Leave unassigned virtreg entries in map 2018-11-07 06:57:03 +00:00
partial-shift-shrink.ll
…
partially-dead-super-register-immediate.ll
…
peephole-opt-regseq-removal.mir [PeepholeOpt] Don't stop simplifying copies on sequence of subregs 2019-03-27 17:27:56 +00:00
pei-reg-scavenger-position.mir [AMDGPU] Extend buffer intrinsics with swizzling 2019-10-02 17:22:36 +00:00
pei-scavenge-sgpr-carry-out.mir AMDGPU: Reuse carry out register during FI elimination 2019-11-28 10:13:48 -08:00
pei-scavenge-sgpr-gfx9.mir AMDGPU: Inline constant when materalizing FI with add on gfx9 2019-09-12 23:46:46 +00:00
pei-scavenge-sgpr.mir AMDGPU: Don't use frame virtual registers 2019-08-29 01:13:47 +00:00
perfhint.ll [AMDGPU] Do not consider indirect acces through phi for wave limiter 2018-06-11 16:50:49 +00:00
permute.ll [AMDGPU] Corrected computeKnownBits for V_PERM_B32 2018-06-13 18:52:54 +00:00
phi-elimination-assertion.mir [AMDGPU]: PHI Elimination hooks added for custom COPY insertion. Fixed 2019-09-17 09:08:58 +00:00
phi-elimination-end-cf.mir AMDGPU: Use SGPR_128 instead of SReg_128 for vregs 2019-10-10 07:11:33 +00:00
pk_max_f16_literal.ll [AMDGPU] gfx1010 allows VOP3 to have a literal 2019-05-02 04:01:39 +00:00
post-ra-sched-kill-bundle-use-inst.mir ScheduleDAG: Fix incorrectly killing registers in bundles 2019-07-05 15:32:28 +00:00
postra-machine-sink.mir PostRA Machine Sink should take care of COPY defining register that is a sub-register by another COPY source operand 2019-12-17 15:20:43 +03:00
postra-norename.mir
…
power-sched-no-instr-sunit.mir [AMDGPU] Extend buffer intrinsics with swizzling 2019-10-02 17:22:36 +00:00
predicate-dp4.ll
…
predicates.ll
…
preserve-hi16.ll AMDGPU: Fix i16 arithmetic pattern redundancy 2019-10-08 17:36:38 +00:00
print-mir-custom-pseudo.ll [AMDGPU] Rename pass "isel" to "amdgpu-isel" 2018-10-03 03:38:22 +00:00
private-access-no-objects.ll
…
private-element-size.ll [FileCheck] Add -allow-deprecated-dag-overlap to failing llvm tests 2018-07-11 20:25:49 +00:00
private-memory-atomics.ll
…
private-memory-r600.ll AMDGPU: Switch backend default max workgroup size to 1024 2019-11-13 07:11:02 +05:30
promote-alloca-addrspacecast.ll AMDGPU: Switch backend default max workgroup size to 1024 2019-11-13 07:11:02 +05:30
promote-alloca-array-aggregate.ll
…
promote-alloca-array-allocation.ll
…
promote-alloca-bitcast-function.ll [AMDGPU] Add a pass to promote bitcast calls 2018-10-26 13:18:36 +00:00
promote-alloca-calling-conv.ll AMDGPU: Remove amdgpu-max-work-group-size attribute 2019-06-05 20:32:32 +00:00
promote-alloca-globals.ll AMDGPU: Write LDS objects out as global symbols in code generation 2019-06-25 11:52:30 +00:00
promote-alloca-invariant-markers.ll AMDGPU: Remove remnants of old address space mapping 2018-08-31 05:49:54 +00:00
promote-alloca-lifetime.ll AMDGPU: Fix iterator crash in AMDGPUPromoteAlloca 2019-06-18 12:23:44 +00:00
promote-alloca-mem-intrinsics.ll Add a 'dynamic' parameter to the objectsize intrinsic 2019-01-30 20:34:35 +00:00
promote-alloca-no-opts.ll AMDGPU: Enable code object v3 for AMDHSA only 2018-11-15 02:32:43 +00:00
promote-alloca-padding-size-estimate.ll AMDGPU: Enable code object v3 for AMDHSA only 2018-11-15 02:32:43 +00:00
promote-alloca-stored-pointer-value.ll
…
promote-alloca-to-lds-icmp.ll AMDGPU: Switch backend default max workgroup size to 1024 2019-11-13 07:11:02 +05:30
promote-alloca-to-lds-phi.ll AMDGPU: Switch backend default max workgroup size to 1024 2019-11-13 07:11:02 +05:30
promote-alloca-to-lds-select.ll AMDGPU: Switch backend default max workgroup size to 1024 2019-11-13 07:11:02 +05:30
promote-alloca-unhandled-intrinsic.ll
…
promote-alloca-vector-to-vector.ll [AMDGPU] Convert insert_vector_elt into set of selects 2018-11-19 17:39:20 +00:00
promote-alloca-volatile.ll
…
promote-constOffset-to-imm-gfx10.mir [AMDGPU] Keep consistent check of legal addressing mode. 2019-11-20 15:08:17 -05:00
promote-constOffset-to-imm.ll [MachineScheduler] Reduce reordering due to mem op clustering 2020-01-14 19:19:02 +00:00
promote-constOffset-to-imm.mir AMDGPU: Use SGPR_128 instead of SReg_128 for vregs 2019-10-10 07:11:33 +00:00
propagate-attributes-bitcast-function.ll [test] Fix tests when run on windows after SVN r369426. NFC. 2019-08-20 20:58:02 +00:00
propagate-attributes-clone.ll [test] Fix tests when run on windows after SVN r369426. NFC. 2019-08-20 20:58:02 +00:00
propagate-attributes-single-set.ll [test] Fix tests when run on windows after SVN r369426. NFC. 2019-08-20 20:58:02 +00:00
pv-packing.ll
…
pv.ll
…
r600-constant-array-fixup.ll Partially revert D61491 "AMDGPU: Be explicit about whether the high-word in SI_PC_ADD_REL_OFFSET is 0" 2019-09-02 14:40:57 +00:00
r600-encoding.ll
…
r600-export-fix.ll [AMDGPU] Automatically generate various tests. NFC 2019-08-23 17:58:49 +00:00
r600-infinite-loop-bug-while-reorganizing-vector.ll
…
r600-legalize-umax-bug.ll
…
r600.add.ll AMDGPU: Select VOP3 form of add 2019-05-08 22:09:57 +00:00
r600.alu-limits.ll
…
r600.amdgpu-alias-analysis.ll [AMDGPU] Add an experimental buffer fat pointer address space. 2019-03-18 14:44:28 +00:00
r600.bitcast.ll
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r600.extract-lowbits.ll AMDGPU: Stop trying to extend arguments for clover 2018-07-28 12:34:25 +00:00
r600.func-alignment.ll
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r600.global_atomics.ll
…
r600.private-memory.ll
…
r600.sub.ll AMDGPU: Select VOP3 form of sub 2019-05-03 15:37:07 +00:00
r600.work-item-intrinsics.ll AMDGPU/R600: Convert kernel param loads to use PARAM_I_ADDRESS 2018-08-01 18:36:07 +00:00
r600cfg.ll
…
rcp-pattern.ll
…
rcp_iflag.ll [AMDGPU] Convert rcp to rcp_iflag 2018-06-27 15:33:33 +00:00
read-register-invalid-subtarget.ll [Support] make report_fatal_error `abort` instead of `exit` 2020-01-15 17:05:13 -08:00
read-register-invalid-type-i32.ll [Support] make report_fatal_error `abort` instead of `exit` 2020-01-15 17:05:13 -08:00
read-register-invalid-type-i64.ll [Support] make report_fatal_error `abort` instead of `exit` 2020-01-15 17:05:13 -08:00
read_register.ll AMDGPU: Adjust test so it will work with GlobalISel 2019-12-27 19:37:39 -05:00
readcyclecounter.ll [AMDGPU] Always use s_memtime for readcyclecounter 2019-07-09 03:10:18 +00:00
readlane_exec0.mir [AMDGPU] gfx1010 VMEM and SMEM implementation 2019-04-30 22:08:23 +00:00
reassoc-scalar.ll [AMDGPU] Fixed hang during DAG combine 2019-02-26 20:56:25 +00:00
reduce-build-vec-ext-to-ext-build-vec.ll AMDGPU: Decompose all values to 32-bit pieces for calling conventions 2019-07-19 13:57:44 +00:00
reduce-load-width-alignment.ll
…
reduce-saveexec.mir [AMDGPU] Add support for immediate operand for S_ENDPGM 2019-03-12 09:52:58 +00:00
reduce-store-width-alignment.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
reduction.ll DAG: Change behavior of fminnum/fmaxnum nodes 2018-10-22 16:27:27 +00:00
reg-coalescer-sched-crash.ll
…
regbank-reassign.mir AMDGPU: Use SGPR_128 instead of SReg_128 for vregs 2019-10-10 07:11:33 +00:00
regcoal-subrange-join-seg.mir AMDGPU: Use SGPR_128 instead of SReg_128 for vregs 2019-10-10 07:11:33 +00:00
regcoal-subrange-join.mir AMDGPU: Use SGPR_128 instead of SReg_128 for vregs 2019-10-10 07:11:33 +00:00
regcoalesce-cannot-join-failures.mir [AMDGPU] Add support for immediate operand for S_ENDPGM 2019-03-12 09:52:58 +00:00
regcoalesce-dbg.mir [AMDGPU] Extend buffer intrinsics with swizzling 2019-10-02 17:22:36 +00:00
regcoalesce-keep-valid-lanes-implicit-def-bug39602.mir [AMDGPU] Add support for immediate operand for S_ENDPGM 2019-03-12 09:52:58 +00:00
regcoalesce-prune.mir [AMDGPU] Add support for immediate operand for S_ENDPGM 2019-03-12 09:52:58 +00:00
regcoalescing-remove-partial-redundancy-assert.mir AMDGPU: Use SGPR_128 instead of SReg_128 for vregs 2019-10-10 07:11:33 +00:00
register-count-comments.ll
…
rename-disconnected-bug.ll
…
rename-independent-subregs-mac-operands.mir [AMDGPU] Extend buffer intrinsics with swizzling 2019-10-02 17:22:36 +00:00
rename-independent-subregs.mir AMDGPU: Use SGPR_128 instead of SReg_128 for vregs 2019-10-10 07:11:33 +00:00
reorder-stores.ll
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reqd-work-group-size.ll
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ret.ll AMDGPU/GlobalISel: Handle most function return types 2019-07-26 02:36:05 +00:00
ret_jump.ll [AMDGPU] Invert the handling of skip insertion. 2020-01-15 15:18:16 +05:30
returnaddress.ll AMDGPU: Return address lowering 2019-05-29 18:20:11 +00:00
rewrite-out-arguments-address-space.ll IR: print value numbers for unnamed function arguments 2019-08-03 14:28:34 +00:00
rewrite-out-arguments.ll IR: print value numbers for unnamed function arguments 2019-08-03 14:28:34 +00:00
rotl.i64.ll
…
rotl.ll
…
rotr.i64.ll
…
rotr.ll
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rsq.ll [DAGCombiner] Improve division estimation of floating points. 2019-09-12 07:51:24 +00:00
rv7x0_count3.ll
…
s_addk_i32.ll AMDGPU: Explicitly define a triple for some tests 2019-06-17 19:25:57 +00:00
s_code_end.ll [AMDGPU] Increase kernel padding 2019-07-24 19:40:13 +00:00
s_movk_i32.ll
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s_mulk_i32.ll AMDGPU: Explicitly define a triple for some tests 2019-06-17 19:25:57 +00:00
sad.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
saddo.ll [AMDGPU] Allow folding of sgpr to vgpr copy 2019-10-23 18:42:48 -07:00
salu-to-valu.ll [DAGCombiner] [CodeGenPrepare] More comprehensive GEP splitting 2019-06-17 10:54:12 +00:00
sampler-resource-id.ll
…
scalar-branch-missing-and-exec.ll
…
scalar-store-cache-flush.mir [AMDGPU] gfx1010 VMEM and SMEM implementation 2019-04-30 22:08:23 +00:00
scalar_to_vector.ll [AMDGPU] Regenerate tests. 2019-07-27 14:32:23 +00:00
scalar_to_vector_v2x16.ll [AMDGPU] Restored selection of scalar_to_vector (v2x16) 2018-11-19 19:58:13 +00:00
sched-assert-dead-def-subreg-use-other-subreg.mir [AMDGPU] Extend buffer intrinsics with swizzling 2019-10-02 17:22:36 +00:00
sched-assert-onlydbg-value-empty-region.mir [AMDGPU] gfx1010 VMEM and SMEM implementation 2019-04-30 22:08:23 +00:00
sched-crash-dbg-value.mir [AMDGPU] Extend buffer intrinsics with swizzling 2019-10-02 17:22:36 +00:00
sched-handleMoveUp-subreg-def-across-subreg-def.mir LiveIntervals: Fix handleMoveUp with subreg def moving across a def 2019-10-18 23:24:25 +00:00
schedule-barrier.mir [AMDGPU] Extend buffer intrinsics with swizzling 2019-10-02 17:22:36 +00:00
schedule-fs-loop-nested-if.ll
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schedule-fs-loop-nested.ll
…
schedule-fs-loop.ll
…
schedule-global-loads.ll
…
schedule-if-2.ll
…
schedule-if.ll
…
schedule-ilp.ll
…
schedule-kernel-arg-loads.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
schedule-regpressure-limit.ll
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schedule-regpressure-limit2.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
schedule-regpressure-limit3.ll
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schedule-regpressure.mir AMDGPU: Use SGPR_128 instead of SReg_128 for vregs 2019-10-10 07:11:33 +00:00
schedule-vs-if-nested-loop-failure.ll [AMDGPU] Remove FeatureVGPRSpilling 2018-10-31 18:54:06 +00:00
schedule-vs-if-nested-loop.ll
…
scheduler-handle-move-bundle.mir [AMDGPU] Fix getInstrLatency() always returning 1 2020-01-14 01:08:30 -08:00
scheduler-subrange-crash.ll AMDGPU: Convert tests away from llvm.SI.load.const 2019-01-17 22:47:26 +00:00
scratch-buffer.ll
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scratch-simple.ll [AMDGPU] Fix bundle scheduling 2020-01-09 15:56:36 -08:00
sdiv.ll [TargetLowering] Add SimplifyMultipleUseDemandedBits 2019-07-23 12:39:08 +00:00
sdivrem24.ll [AMDGPU] Convert rcp to rcp_iflag 2018-06-27 15:33:33 +00:00
sdivrem64.ll
…
sdwa-gfx9.mir [AMDGPU] gfx1010 VMEM and SMEM implementation 2019-04-30 22:08:23 +00:00
sdwa-op64-test.ll [AMDGPU] Add sdwa support for ADD|SUB U64 decomposed Pseudos 2018-12-03 13:04:54 +00:00
sdwa-ops.mir [AMDGPU] gfx1010 VMEM and SMEM implementation 2019-04-30 22:08:23 +00:00
sdwa-peephole-instr-gfx10.mir [AMDGPU] gfx1010: use fmac instructions 2019-05-04 04:20:37 +00:00
sdwa-peephole-instr.mir [AMDGPU] gfx1010 VMEM and SMEM implementation 2019-04-30 22:08:23 +00:00
sdwa-peephole.ll AMDGPU: Fix not using v_cvt_f16_[iu]16 2020-01-07 15:10:07 -05:00
sdwa-preserve.mir [AMDGPU] gfx1010 VMEM and SMEM implementation 2019-04-30 22:08:23 +00:00
sdwa-scalar-ops.mir [Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing 2019-09-11 11:16:48 +00:00
sdwa-vop2-64bit.mir [AMDGPU] gfx1010 VMEM and SMEM implementation 2019-04-30 22:08:23 +00:00
select-fabs-fneg-extract-legacy.ll
…
select-fabs-fneg-extract.ll [AMDGPU] Allow abs/neg source modifiers on v_cndmask_b32 2019-07-10 14:53:47 +00:00
select-i1.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
select-opt.ll [AMDGPU] Come back patch for the 'Assign register class for cross block values according to the divergence.' 2019-10-14 12:01:10 +00:00
select-undef.ll Moved dag-combine-select-undef.ll into amdgpu. NFC. 2018-11-17 00:17:15 +00:00
select-vectors.ll [AMDGPU] Added v5i32 and v5f32 register classes 2019-03-22 10:11:21 +00:00
select.f16.ll [codegen,amdgpu] Enhance MIR DIE and re-arrange it for AMDGPU. 2020-01-14 19:26:15 -05:00
select.ll
…
select64.ll
…
selectcc-cnd.ll
…
selectcc-cnde-int.ll
…
selectcc-icmp-select-float.ll
…
selectcc-opt.ll [AMDGPU] Fix bundle scheduling 2020-01-09 15:56:36 -08:00
selectcc.ll
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sendmsg-m0-hazard.mir [AMDGPU] Add support for immediate operand for S_ENDPGM 2019-03-12 09:52:58 +00:00
set-dx10.ll
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setcc-equivalent.ll
…
setcc-fneg-constant.ll
…
setcc-limit-load-shrink.ll Check shouldReduceLoadWidth from SimplifySetCC 2018-10-31 21:24:30 +00:00
setcc-opt.ll [AMDGPU] Fix bundle scheduling 2020-01-09 15:56:36 -08:00
setcc-sext.ll
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setcc.ll AMDGPU: Remove remnants of old address space mapping 2018-08-31 05:49:54 +00:00
setcc64.ll
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seto.ll
…
setuo.ll
…
sext-eliminate.ll
…
sext-in-reg-failure-r600.ll
…
sext-in-reg.ll AMDGPU: Remove remnants of old address space mapping 2018-08-31 05:49:54 +00:00
sgpr-control-flow.ll [AMDGPU] Come back patch for the 'Assign register class for cross block values according to the divergence.' 2019-10-14 12:01:10 +00:00
sgpr-copy-duplicate-operand.ll
…
sgpr-copy.ll [AMDGPU] Come back patch for the 'Assign register class for cross block values according to the divergence.' 2019-10-14 12:01:10 +00:00
sgpr-spill-wrong-stack-id.mir AMDGPU: Correct properties for adjcallstack* pseudos 2019-07-01 22:01:05 +00:00
sgprcopies.ll
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shader-addr64-nonuniform.ll [AMDGPU] Support for v3i32/v3f32 2019-03-21 12:01:21 +00:00
shared-op-cycle.ll
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shift-and-i64-ubfe.ll [DAGCombine] Prune unnused nodes. 2019-03-29 17:35:56 +00:00
shift-and-i128-ubfe.ll
…
shift-i64-opts.ll [DAGCombine] Prune unnused nodes. 2019-03-29 17:35:56 +00:00
shift-i128.ll [MachineScheduler] Reduce reordering due to mem op clustering 2020-01-14 19:19:02 +00:00
shl-add-to-add-shl.ll
…
shl.ll [SelectionDAG] ComputeKnownBits - minimum leading/trailing zero bits in LSHR/SHL (PR44526) 2020-01-13 11:08:12 +00:00
shl.v2i16.ll [SelectionDAG] ComputeKnownBits - minimum leading/trailing zero bits in LSHR/SHL (PR44526) 2020-01-13 11:08:12 +00:00
shl_add.ll [AMDGPU] gfx1010 core wave32 changes 2019-06-20 15:08:34 +00:00
shl_add_constant.ll [DAG] Refactor DAGCombiner::ReassociateOps 2019-04-29 17:50:10 +00:00
shl_add_ptr.ll [AMDGPU] Fix typo in SIInstrInfo::memOpsHaveSameBasePtr 2019-12-17 18:54:27 +00:00
shl_or.ll [AMDGPU] gfx1010 core wave32 changes 2019-06-20 15:08:34 +00:00
shrink-add-sub-constant.ll AMDGPU: Apply i16 add->sub pattern with zext to i32 2020-01-07 16:36:31 -05:00
shrink-carry.mir [AMDGPU] gfx1010 VMEM and SMEM implementation 2019-04-30 22:08:23 +00:00
shrink-vop3-carry-out.mir [AMDGPU] Extend buffer intrinsics with swizzling 2019-10-02 17:22:36 +00:00
si-annotate-cf-noloop.ll [AMDGPU] Invert the handling of skip insertion. 2020-01-15 15:18:16 +05:30
si-annotate-cf-unreachable.ll [AMDGPU] gfx1010 wave32 icmp/fcmp intrinsic changes for wave32 2019-06-13 23:47:36 +00:00
si-annotate-cf.ll [AMDGPU] Fix emitIfBreak CF lowering: use temp reg to make register coalescer life easier. 2019-11-26 18:59:37 +03:00
si-annotate-cfg-loop-assert.ll
…
si-annotatecfg-multiple-backedges.ll [AMDGPU] gfx1010 wave32 icmp/fcmp intrinsic changes for wave32 2019-06-13 23:47:36 +00:00
si-fix-sgpr-copies.mir [AMDGPU] Come back patch for the 'Assign register class for cross block values according to the divergence.' 2019-10-14 12:01:10 +00:00
si-i1-copies.mir MachineSSAUpdater: insert IMPLICIT_DEF at top of basic block 2019-10-08 12:46:20 +00:00
si-instr-info-correct-implicit-operands.ll Rename ExpandISelPseudo->FinalizeISel, delay register reservation 2019-06-19 00:25:39 +00:00
si-lower-control-flow-kill.ll
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si-lower-control-flow-unreachable-block.ll [AMDGPU] Invert the handling of skip insertion. 2020-01-15 15:18:16 +05:30
si-lower-control-flow.mir [AMDGPU] Invert the handling of skip insertion. 2020-01-15 15:18:16 +05:30
si-lower-i1-copies.mir AMDGPU: Fix LCSSA phi lowering in SILowerI1Copies 2019-04-23 13:12:52 +00:00
si-lower-sgpr-spills.mir [AMDGPU] Add test case on crashing of `si-lower-sgpr-spills` pass 2019-07-19 18:50:53 +00:00
si-scheduler.ll AMDGPU: Decompose all values to 32-bit pieces for calling conventions 2019-07-19 13:57:44 +00:00
si-sgpr-spill.ll AMDGPU: Drop remnants of byval support for shaders 2019-07-12 20:12:17 +00:00
si-spill-cf.ll AMDGPU: Convert tests away from llvm.SI.load.const 2019-01-17 22:47:26 +00:00
si-spill-sgpr-stack.ll [AMDGPU] Remove -amdgpu-spill-sgpr-to-smem. 2019-10-18 21:48:22 +00:00
si-triv-disjoint-mem-access.ll [AMDGPU] Disable SReg Global LD/ST, perf regression 2018-11-30 18:29:17 +00:00
si-vector-hang.ll
…
sibling-call.ll AMDGPU: Make s34 the FP register 2019-07-08 19:03:38 +00:00
sign_extend.ll AMDGPU: Don't use the default cpu in a few tests 2019-04-03 00:00:58 +00:00
simplify-libcalls.ll Revert "Revert "As a follow-up to my initial mail to llvm-dev here's a first pass at the O1 described there."" 2019-11-26 20:28:52 -08:00
simplifydemandedbits-recursion.ll
…
sint_to_fp.f64.ll AMDGPU: Add run line to int_to_fp tests 2020-01-06 21:38:50 -05:00
sint_to_fp.i64.ll [AMDGPU] Allow abs/neg source modifiers on v_cndmask_b32 2019-07-10 14:53:47 +00:00
sint_to_fp.ll [AMDGPU] Fix bundle scheduling 2020-01-09 15:56:36 -08:00
sitofp.f16.ll AMDGPU: Fix not using v_cvt_f16_[iu]16 2020-01-07 15:10:07 -05:00
skip-branch-taildup-ret.mir [AMDGPU] Invert the handling of skip insertion. 2020-01-15 15:18:16 +05:30
skip-branch-trap.ll [AMDGPU] Invert the handling of skip insertion. 2020-01-15 15:18:16 +05:30
skip-if-dead.ll [AMDGPU] Invert the handling of skip insertion. 2020-01-15 15:18:16 +05:30
smed3.ll Reapply [ValueTracking] Support min/max selects in computeConstantRange() 2019-04-07 17:22:16 +00:00
smem-no-clause-coalesced.mir [Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing 2019-09-11 11:16:48 +00:00
smem-war-hazard.mir AMDGPU: Fix SMEM WAR hazard for gfx10 readlane 2019-10-18 18:20:30 +00:00
sminmax.ll [AMDGPU] Unnecessary -amdgpu-scalarize-global-loads=false flag removed from min/max lit tests. 2019-09-19 16:44:38 +00:00
sminmax.v2i16.ll [AMDGPU] Unnecessary -amdgpu-scalarize-global-loads=false flag removed from min/max lit tests. 2019-09-19 16:44:38 +00:00
smrd-fold-offset.mir [AMDGPU] gfx1010 VMEM and SMEM implementation 2019-04-30 22:08:23 +00:00
smrd-gfx10.ll AMDGPU/GFX10: Support DLC bit in llvm.amdgcn.s.buffer.load intrinsic 2019-06-16 17:14:12 +00:00
smrd-vccz-bug.ll [AMDGPU] Simplify VCCZ bug handling 2019-10-30 17:09:07 +00:00
smrd.ll [AMDGPU] Come back patch for the 'Assign register class for cross block values according to the divergence.' 2019-10-14 12:01:10 +00:00
smrd_vmem_war.ll [AMDGPU] Invert the handling of skip insertion. 2020-01-15 15:18:16 +05:30
sopk-compares.ll AMDGPU: Explicitly define a triple for some tests 2019-06-17 19:25:57 +00:00
sp-too-many-input-sgprs.ll AMDGPU: Invert frame index offset interpretation 2019-06-05 22:20:47 +00:00
spill-agpr.ll [AMDGPU] use v32f32 for 3 mfma intrinsics 2019-07-12 22:42:01 +00:00
spill-alloc-sgpr-init-bug.ll
…
spill-before-exec.mir AMDGPU: Use SGPR_128 instead of SReg_128 for vregs 2019-10-10 07:11:33 +00:00
spill-cfg-position.ll AMDGPU: Assume xnack is enabled by default 2019-05-16 14:48:34 +00:00
spill-csr-frame-ptr-reg-copy.ll AMDGPU: Make s34 the FP register 2019-07-08 19:03:38 +00:00
spill-empty-live-interval.mir AMDGPU: Invert frame index offset interpretation 2019-06-05 22:20:47 +00:00
spill-m0.ll [AMDGPU] Remove -amdgpu-spill-sgpr-to-smem. 2019-10-18 21:48:22 +00:00
spill-offset-calculation.ll AMDGPU: Make s34 the FP register 2019-07-08 19:03:38 +00:00
spill-scavenge-offset.ll
…
spill-vgpr-to-agpr.ll [codegen,amdgpu] Enhance MIR DIE and re-arrange it for AMDGPU. 2020-01-14 19:26:15 -05:00
spill-wide-sgpr.ll [AMDGPU] Remove -amdgpu-spill-sgpr-to-smem. 2019-10-18 21:48:22 +00:00
split-arg-dbg-value.ll [AMDGPU] Remove update_llc_test_checks for a test 2019-10-25 11:47:33 -04:00
split-scalar-i64-add.ll CodeGen: Make computeRegisterLiveness consider successors 2018-08-30 07:17:51 +00:00
split-smrd.ll AMDGPU: Drop remnants of byval support for shaders 2019-07-12 20:12:17 +00:00
split-vector-memoperand-offsets.ll
…
splitkit.mir AMDGPU: Use SGPR_128 instead of SReg_128 for vregs 2019-10-10 07:11:33 +00:00
sra.ll AMDGPU: Remove remnants of old address space mapping 2018-08-31 05:49:54 +00:00
sram-ecc-default.ll AMDGPU: Assume ECC is enabled by default if supported 2019-04-03 01:58:57 +00:00
srem.ll [AMDGPU] gfx1010: prefer V_MUL_LO_U32 over V_MUL_LO_I32 2019-05-06 22:27:05 +00:00
srl.ll [FileCheck] Add -allow-deprecated-dag-overlap to failing llvm tests 2018-07-11 20:25:49 +00:00
ssubo.ll [CodeGen] Handle vector UADDO, SADDO, USUBO, SSUBO 2019-02-07 21:02:22 +00:00
stack-pointer-offset-relative-frameindex.ll [AMDGPU] Invert the handling of skip insertion. 2020-01-15 15:18:16 +05:30
stack-realign-kernel.ll [AMDGPU] Clean up update_llc_test_checks CodeGen tests 2019-10-24 17:35:33 -04:00
stack-realign.ll AMDGPU: Make s34 the FP register 2019-07-08 19:03:38 +00:00
stack-size-overflow.ll
…
stack-slot-color-sgpr-vgpr-spills.mir AMDGPU: Stop adding m0 implicit def to SGPR spills 2019-10-21 19:42:29 +00:00
store-barrier.ll
…
store-global.ll [AMDGPU] Support for v3i32/v3f32 2019-03-21 12:01:21 +00:00
store-hi16.ll AMDGPU: Split flat offsets that don't fit in DAG 2019-10-20 17:34:44 +00:00
store-local.ll AMDGPU: Remove remnants of old address space mapping 2018-08-31 05:49:54 +00:00
store-private.ll AMDGPU: Stop trying to extend arguments for clover 2018-07-28 12:34:25 +00:00
store-v3i64.ll [AMDGPU] Fix dwordx3/southern-islands failures. 2019-01-10 16:21:08 +00:00
store-vector-ptrs.ll
…
store-weird-sizes.ll [AMDGPU] Reapplied BFE canonicalization from D60462 2019-05-08 15:49:10 +00:00
store_typed.ll
…
stress-calls.ll Reapply "AMDGPU: Force inlining if LDS global address is used" 2018-07-10 14:03:41 +00:00
structurize.ll
…
structurize1.ll
…
sub-zext-cc-zext-cc.ll Revert "AMDGPU: Try to commute sub of boolean ext" 2019-12-13 12:49:06 +00:00
sub.i16.ll [AMDGPU] Fix bundle scheduling 2020-01-09 15:56:36 -08:00
sub.ll AMDGPU: Select VOP3 form of sub 2019-05-03 15:37:07 +00:00
sub.v2i16.ll AMDGPU: Apply i16 add->sub pattern with zext to i32 2020-01-07 16:36:31 -05:00
sub_i1.ll [AMDGPU] gfx1010 core wave32 changes 2019-06-20 15:08:34 +00:00
subreg-coalescer-crash.ll AMDGPU: Convert test cases to the dimension-aware intrinsics 2018-06-21 13:37:19 +00:00
subreg-coalescer-undef-use.ll [AMDGPU] Invert the handling of skip insertion. 2020-01-15 15:18:16 +05:30
subreg-eliminate-dead.ll
…
subreg-intervals.mir
…
subreg-split-live-in-error.mir AMDGPU: Use SGPR_128 instead of SReg_128 for vregs 2019-10-10 07:11:33 +00:00
subreg-undef-def-with-other-subreg-defs.mir MachineScheduler: Fix missing dependency with multiple subreg defs 2019-09-20 00:09:15 +00:00
subreg_interference.mir AMDGPU: Use SGPR_128 instead of SReg_128 for vregs 2019-10-10 07:11:33 +00:00
subvector-test.mir AMDGPU: Use SGPR_128 instead of SReg_128 for vregs 2019-10-10 07:11:33 +00:00
swizzle-export.ll
…
syncscopes.ll [AMDGPU] gfx1010 VMEM and SMEM implementation 2019-04-30 22:08:23 +00:00
tail-call-cgp.ll
…
tail-dup-bundle.mir Process BUNDLE in tail duplication 2020-01-15 15:46:57 -08:00
tail-duplication-convergent.ll AMDGPU: Add intrinsics for DS GWS semaphore instructions 2019-06-20 21:11:42 +00:00
target-cpu.ll AMDGPU: Write LDS objects out as global symbols in code generation 2019-06-25 11:52:30 +00:00
tex-clause-antidep.ll
…
texture-input-merge.ll
…
trap.ll
…
trunc-bitcast-vector.ll [AMDGPU] combine extractelement into several selects 2018-11-13 21:18:21 +00:00
trunc-cmp-constant.ll
…
trunc-combine.ll [AMDGPU] Fix typo in SIInstrInfo::memOpsHaveSameBasePtr 2019-12-17 18:54:27 +00:00
trunc-store-f64-to-f16.ll
…
trunc-store-i1.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
trunc-store.ll
…
trunc-vector-store-assertion-failure.ll AMDGPU: Remove remnants of old address space mapping 2018-08-31 05:49:54 +00:00
trunc.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
tti-unroll-prefs.ll
…
twoaddr-fma.mir [AMDGPU] Allow FP inline constant in v_madak_f16 and v_fmaak_f16 2019-09-18 09:32:06 +00:00
twoaddr-mad.mir [AMDGPU] Allow FP inline constant in v_madak_f16 and v_fmaak_f16 2019-09-18 09:32:06 +00:00
uaddo.ll AMDGPU: Fix capitalized register names in asm constraints 2019-06-14 21:16:06 +00:00
udiv.ll [AMDGPU] Preliminary patch for divergence driven instruction selection. Immediate selection predicate changed 2018-09-11 11:56:50 +00:00
udivrem.ll [AMDGPU] gfx1010: prefer V_MUL_LO_U32 over V_MUL_LO_I32 2019-05-06 22:27:05 +00:00
udivrem24.ll [AMDGPU] V_CVT_F32_UBYTE{0,1,2,3} are full rate instructions 2019-03-08 09:03:11 +00:00
udivrem64.ll [AMDGPU] Fix SGPR fixing through SCC chaining 2019-03-15 12:42:21 +00:00
uint_to_fp.f64.ll AMDGPU: Fix not using v_cvt_f16_[iu]16 2020-01-07 15:10:07 -05:00
uint_to_fp.i64.ll
…
uint_to_fp.ll [AMDGPU] Fix bundle scheduling 2020-01-09 15:56:36 -08:00
uitofp.f16.ll AMDGPU: Fix not using v_cvt_f16_[iu]16 2020-01-07 15:10:07 -05:00
umed3.ll Reapply [ValueTracking] Support min/max selects in computeConstantRange() 2019-04-07 17:22:16 +00:00
unaligned-load-store.ll DAG: Fix expansion of unaligned FP loads and stores 2018-09-13 12:14:23 +00:00
undefined-physreg-sgpr-spill.mir [Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing 2019-09-11 11:16:48 +00:00
undefined-subreg-liverange.ll [SchedModel] Fix for read advance cycles with implicit pseudo operands. 2018-10-30 15:04:40 +00:00
unhandled-loop-condition-assertion.ll
…
uniform-branch-intrinsic-cond.ll
…
uniform-cfg.ll [AMDGPU] Invert the handling of skip insertion. 2020-01-15 15:18:16 +05:30
uniform-crash.ll
…
uniform-loop-inside-nonuniform.ll [AMDGPU] Invert the handling of skip insertion. 2020-01-15 15:18:16 +05:30
uniform-work-group-attribute-missing.ll AMDGPU: Handle "uniform-work-group-size" attribute (fix for RADV) 2019-03-07 00:54:04 +00:00
uniform-work-group-nested-function-calls.ll AMDGPU: Handle "uniform-work-group-size" attribute (fix for RADV) 2019-03-07 00:54:04 +00:00
uniform-work-group-prevent-attribute-propagation.ll AMDGPU: Handle "uniform-work-group-size" attribute (fix for RADV) 2019-03-07 00:54:04 +00:00
uniform-work-group-propagate-attribute.ll AMDGPU: Handle "uniform-work-group-size" attribute (fix for RADV) 2019-03-07 00:54:04 +00:00
uniform-work-group-recursion-test.ll AMDGPU: Handle "uniform-work-group-size" attribute (fix for RADV) 2019-03-07 00:54:04 +00:00
uniform-work-group-test.ll AMDGPU: Handle "uniform-work-group-size" attribute (fix for RADV) 2019-03-07 00:54:04 +00:00
unify-metadata.ll
…
unigine-liveness-crash.ll AMDGPU: Drop remnants of byval support for shaders 2019-07-12 20:12:17 +00:00
unknown-processor.ll AMDGPU: Remove remnants of old address space mapping 2018-08-31 05:49:54 +00:00
unpack-half.ll
…
unroll.ll AMDGPU: Fix tests using the default alloca address space 2019-07-01 15:23:03 +00:00
unsupported-calls.ll AMDGPU: Don't error on calls to null or undef 2019-10-20 07:46:04 +00:00
unsupported-cc.ll
…
update-phi.ll Update phis in AMDGPUUnifyDivergentExitNodes 2019-06-25 18:55:16 +00:00
urem.ll [AMDGPU] gfx1010: prefer V_MUL_LO_U32 over V_MUL_LO_I32 2019-05-06 22:27:05 +00:00
use-sgpr-multiple-times.ll [AMDGPU] Come back patch for the 'Assign register class for cross block values according to the divergence.' 2019-10-14 12:01:10 +00:00
usubo.ll AMDGPU: Fix capitalized register names in asm constraints 2019-06-14 21:16:06 +00:00
v1i64-kernel-arg.ll
…
v1024.ll [AMDGPU] Change register type for v32 vectors 2019-07-16 20:06:00 +00:00
v_cndmask.ll [AMDGPU] Restrict v_cndmask_b32 abs/neg modifiers to f32 2019-07-12 15:02:59 +00:00
v_cvt_pk_u8_f32.ll
…
v_mac.ll [AMDGPU] Support for v3i32/v3f32 2019-03-21 12:01:21 +00:00
v_mac_f16.ll [AMDGPU] Mark s_barrier as having side effects but not accessing memory. 2019-09-06 10:07:28 +00:00
v_madak_f16.ll AMDGPU: Don't use the default cpu in a few tests 2019-04-03 00:00:58 +00:00
v_swap_b32.mir [AMDGPU] Add support for immediate operand for S_ENDPGM 2019-03-12 09:52:58 +00:00
valu-i1.ll [AMDGPU] Invert the handling of skip insertion. 2020-01-15 15:18:16 +05:30
vccz-corrupt-bug-workaround.mir [AMDGPU] Extend buffer intrinsics with swizzling 2019-10-02 17:22:36 +00:00
vcmpx-exec-war-hazard.mir [AMDGPU] more gfx1010 tests. NFC. 2019-06-12 18:44:11 +00:00
vcmpx-permlane-hazard.mir [AMDGPU] gfx1010 premlane instructions 2019-06-12 17:52:51 +00:00
vector-alloca-addrspacecast.ll
…
vector-alloca-atomic.ll
…
vector-alloca.ll AMDGPU: Remove remnants of old address space mapping 2018-08-31 05:49:54 +00:00
vector-extract-insert.ll [AMDGPU] Convert insert_vector_elt into set of selects 2018-11-19 17:39:20 +00:00
vector-legalizer-divergence.ll
…
vector_shuffle.packed.ll [AMDGPU] Fix typo in SIInstrInfo::memOpsHaveSameBasePtr 2019-12-17 18:54:27 +00:00
vectorize-buffer-fat-pointer.ll [AMDGPU] Add an experimental buffer fat pointer address space. 2019-03-18 14:44:28 +00:00
vectorize-global-local.ll
…
verify-sop.mir [Support] make report_fatal_error `abort` instead of `exit` 2020-01-15 17:05:13 -08:00
vertex-fetch-encoding.ll
…
vgpr-descriptor-waterfall-loop-idom-update.ll [MachineScheduler] Reduce reordering due to mem op clustering 2020-01-14 19:19:02 +00:00
vgpr-spill-emergency-stack-slot-compute.ll [AMDGPU] Come back patch for the 'Assign register class for cross block values according to the divergence.' 2019-10-14 12:01:10 +00:00
vgpr-spill-emergency-stack-slot.ll AMDGPU: Drop remnants of byval support for shaders 2019-07-12 20:12:17 +00:00
vi-removed-intrinsics.ll Reapply "Adapt gcov to changes in CFE." 2018-12-06 18:44:48 +00:00
virtregrewrite-undef-identity-copy.mir AMDGPU: Correct properties for adjcallstack* pseudos 2019-07-01 22:01:05 +00:00
vmem-to-salu-hazard.mir [AMDGPU] Extend buffer intrinsics with swizzling 2019-10-02 17:22:36 +00:00
vmem-vcc-hazard.mir [AMDGPU] Extend buffer intrinsics with swizzling 2019-10-02 17:22:36 +00:00
vop-shrink-frame-index.mir [AMDGPU] Asm/disasm clamp modifier on vop3 int arithmetic 2019-03-18 19:35:44 +00:00
vop-shrink-non-ssa.mir [AMDGPU] Asm/disasm clamp modifier on vop3 int arithmetic 2019-03-18 19:35:44 +00:00
vop-shrink.ll
…
vselect.ll
…
vselect64.ll
…
vtx-fetch-branch.ll
…
vtx-schedule.ll
…
wait.ll [AMDGPU] Fix typo in SIInstrInfo::memOpsHaveSameBasePtr 2019-12-17 18:54:27 +00:00
waitcnt-back-edge-loop.mir [AMDGPU] gfx1010 VMEM and SMEM implementation 2019-04-30 22:08:23 +00:00
waitcnt-debug.mir
…
waitcnt-flat.ll
…
waitcnt-loop-irreducible.mir [AMDGPU] Extend buffer intrinsics with swizzling 2019-10-02 17:22:36 +00:00
waitcnt-loop-single-basic-block.mir [AMDGPU] gfx1010 VMEM and SMEM implementation 2019-04-30 22:08:23 +00:00
waitcnt-looptest.ll AMDGPU: Rewrite SILowerI1Copies to always stay on SALU 2018-10-31 13:27:08 +00:00
waitcnt-no-redundant.mir
…
waitcnt-overflow.mir AMDGPU: Handle waitcnt overflow 2019-11-23 09:34:23 -08:00
waitcnt-permute.mir
…
waitcnt-preexisting.mir [AMDGPU] gfx1010 VMEM and SMEM implementation 2019-04-30 22:08:23 +00:00
waitcnt-vscnt.ll [AMDGPU] Mark s_barrier as having side effects but not accessing memory. 2019-09-06 10:07:28 +00:00
waitcnt-vscnt.mir [amdgpu] Fix scoreboard updating on `s_waitcnt_vscnt`. 2019-12-31 14:20:30 -05:00
waitcnt.mir AMDGPU: Look through bundles for existing waitcnts 2019-07-03 00:30:44 +00:00
wave32.ll [AMDGPU] Invert the handling of skip insertion. 2020-01-15 15:18:16 +05:30
wave_dispatch_regs.ll
…
widen-smrd-loads.ll [DAG] Refactor DAGCombiner::ReassociateOps 2019-04-29 17:50:10 +00:00
widen-vselect-and-mask.ll
…
widen_extending_scalar_loads.ll
…
wqm.ll [AMDGPU] Invert the handling of skip insertion. 2020-01-15 15:18:16 +05:30
wqm.mir [AMDGPU] Remove unnecessary v_mov from a register to itself in WQM lowering. 2020-01-10 23:01:19 -05:00
write-register-vgpr-into-sgpr.ll
…
write_register.ll AMDGPU: Split test function 2020-01-12 22:44:51 -05:00
wrong-transalu-pos-fix.ll
…
wwm-reserved.ll AMDGPU: Decompose all values to 32-bit pieces for calling conventions 2019-07-19 13:57:44 +00:00
xfail.r600.bitcast.ll
…
xnor.ll [AMDGPU] Split 64-Bit XNOR to 64-Bit NOT/XOR 2018-12-01 12:27:53 +00:00
xor.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
xor3-i1-const.ll [AMDGPU] Fixed handling of imemdiate i1 literals 2019-05-14 16:18:00 +00:00
xor3.ll [AMDGPU] gfx1010 core wave32 changes 2019-06-20 15:08:34 +00:00
xor_add.ll [AMDGPU] gfx1010 core wave32 changes 2019-06-20 15:08:34 +00:00
zero_extend.ll [AMDGPU] Fix bundle scheduling 2020-01-09 15:56:36 -08:00
zext-i64-bit-operand.ll
…
zext-lid.ll [AMDGPU] Packed thread ids in function call ABI 2019-06-28 01:52:13 +00:00

README 

+==============================================================================+
| How to organize the lit tests                                                |
+==============================================================================+

- If you write a test for matching a single DAG opcode or intrinsic, it should
  go in a file called {opcode_name,intrinsic_name}.ll (e.g. fadd.ll)

- If you write a test that matches several DAG opcodes and checks for a single
  ISA instruction, then that test should go in a file called {ISA_name}.ll (e.g.
  bfi_int.ll

- For all other tests, use your best judgement for organizing tests and naming
  the files.

+==============================================================================+
| Naming conventions                                                           |
+==============================================================================+

- Use dash '-' and not underscore '_' to separate words in file names, unless
  the file is named after a DAG opcode or ISA instruction that has an
  underscore '_' in its name.