forked from OSchip/llvm-project
157 lines
6.3 KiB
YAML
157 lines
6.3 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=x86_64-linux-gnu -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=NO_AVX512VL --check-prefix=NO_AVX512F --check-prefix=SSE
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# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=NO_AVX512VL --check-prefix=NO_AVX512F --check-prefix=AVX
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# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx512f -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=NO_AVX512VL --check-prefix=AVX512ALL --check-prefix=AVX512F
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# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx512f -mattr=+avx512vl -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=AVX512ALL --check-prefix=AVX512VL
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--- |
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define float @test_fmul_float(float %arg1, float %arg2) {
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%ret = fmul float %arg1, %arg2
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ret float %ret
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}
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define double @test_fmul_double(double %arg1, double %arg2) {
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%ret = fmul double %arg1, %arg2
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ret double %ret
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}
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...
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---
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name: test_fmul_float
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alignment: 4
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legalized: true
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regBankSelected: true
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#
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registers:
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- { id: 0, class: vecr, preferred-register: '' }
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- { id: 1, class: vecr, preferred-register: '' }
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- { id: 2, class: vecr, preferred-register: '' }
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- { id: 3, class: vecr, preferred-register: '' }
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- { id: 4, class: vecr, preferred-register: '' }
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- { id: 5, class: vecr, preferred-register: '' }
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liveins:
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fixedStack:
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stack:
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constants:
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#
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#
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body: |
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bb.1 (%ir-block.0):
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liveins: $xmm0, $xmm1
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; SSE-LABEL: name: test_fmul_float
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; SSE: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
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; SSE: [[COPY1:%[0-9]+]]:fr32 = COPY [[COPY]]
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; SSE: [[COPY2:%[0-9]+]]:vr128 = COPY $xmm1
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; SSE: [[COPY3:%[0-9]+]]:fr32 = COPY [[COPY2]]
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; SSE: [[MULSSrr:%[0-9]+]]:fr32 = MULSSrr [[COPY1]], [[COPY3]]
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; SSE: [[COPY4:%[0-9]+]]:vr128 = COPY [[MULSSrr]]
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; SSE: $xmm0 = COPY [[COPY4]]
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; SSE: RET 0, implicit $xmm0
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; AVX-LABEL: name: test_fmul_float
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; AVX: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
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; AVX: [[COPY1:%[0-9]+]]:fr32 = COPY [[COPY]]
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; AVX: [[COPY2:%[0-9]+]]:vr128 = COPY $xmm1
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; AVX: [[COPY3:%[0-9]+]]:fr32 = COPY [[COPY2]]
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; AVX: [[VMULSSrr:%[0-9]+]]:fr32 = VMULSSrr [[COPY1]], [[COPY3]]
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; AVX: [[COPY4:%[0-9]+]]:vr128 = COPY [[VMULSSrr]]
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; AVX: $xmm0 = COPY [[COPY4]]
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; AVX: RET 0, implicit $xmm0
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; AVX512F-LABEL: name: test_fmul_float
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; AVX512F: [[COPY:%[0-9]+]]:vr128x = COPY $xmm0
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; AVX512F: [[COPY1:%[0-9]+]]:fr32x = COPY [[COPY]]
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; AVX512F: [[COPY2:%[0-9]+]]:vr128x = COPY $xmm1
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; AVX512F: [[COPY3:%[0-9]+]]:fr32x = COPY [[COPY2]]
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; AVX512F: [[VMULSSZrr:%[0-9]+]]:fr32x = VMULSSZrr [[COPY1]], [[COPY3]]
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; AVX512F: [[COPY4:%[0-9]+]]:vr128x = COPY [[VMULSSZrr]]
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; AVX512F: $xmm0 = COPY [[COPY4]]
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; AVX512F: RET 0, implicit $xmm0
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; AVX512VL-LABEL: name: test_fmul_float
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; AVX512VL: [[COPY:%[0-9]+]]:vr128x = COPY $xmm0
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; AVX512VL: [[COPY1:%[0-9]+]]:fr32x = COPY [[COPY]]
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; AVX512VL: [[COPY2:%[0-9]+]]:vr128x = COPY $xmm1
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; AVX512VL: [[COPY3:%[0-9]+]]:fr32x = COPY [[COPY2]]
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; AVX512VL: [[VMULSSZrr:%[0-9]+]]:fr32x = VMULSSZrr [[COPY1]], [[COPY3]]
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; AVX512VL: [[COPY4:%[0-9]+]]:vr128x = COPY [[VMULSSZrr]]
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; AVX512VL: $xmm0 = COPY [[COPY4]]
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; AVX512VL: RET 0, implicit $xmm0
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%2:vecr(s128) = COPY $xmm0
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%0:vecr(s32) = G_TRUNC %2(s128)
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%3:vecr(s128) = COPY $xmm1
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%1:vecr(s32) = G_TRUNC %3(s128)
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%4:vecr(s32) = G_FMUL %0, %1
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%5:vecr(s128) = G_ANYEXT %4(s32)
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$xmm0 = COPY %5(s128)
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RET 0, implicit $xmm0
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...
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---
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name: test_fmul_double
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alignment: 4
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legalized: true
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regBankSelected: true
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#
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registers:
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- { id: 0, class: vecr, preferred-register: '' }
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- { id: 1, class: vecr, preferred-register: '' }
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- { id: 2, class: vecr, preferred-register: '' }
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- { id: 3, class: vecr, preferred-register: '' }
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- { id: 4, class: vecr, preferred-register: '' }
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- { id: 5, class: vecr, preferred-register: '' }
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liveins:
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fixedStack:
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stack:
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constants:
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#
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#
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body: |
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bb.1 (%ir-block.0):
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liveins: $xmm0, $xmm1
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; SSE-LABEL: name: test_fmul_double
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; SSE: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
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; SSE: [[COPY1:%[0-9]+]]:fr64 = COPY [[COPY]]
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; SSE: [[COPY2:%[0-9]+]]:vr128 = COPY $xmm1
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; SSE: [[COPY3:%[0-9]+]]:fr64 = COPY [[COPY2]]
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; SSE: [[MULSDrr:%[0-9]+]]:fr64 = MULSDrr [[COPY1]], [[COPY3]]
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; SSE: [[COPY4:%[0-9]+]]:vr128 = COPY [[MULSDrr]]
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; SSE: $xmm0 = COPY [[COPY4]]
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; SSE: RET 0, implicit $xmm0
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; AVX-LABEL: name: test_fmul_double
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; AVX: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
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; AVX: [[COPY1:%[0-9]+]]:fr64 = COPY [[COPY]]
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; AVX: [[COPY2:%[0-9]+]]:vr128 = COPY $xmm1
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; AVX: [[COPY3:%[0-9]+]]:fr64 = COPY [[COPY2]]
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; AVX: [[VMULSDrr:%[0-9]+]]:fr64 = VMULSDrr [[COPY1]], [[COPY3]]
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; AVX: [[COPY4:%[0-9]+]]:vr128 = COPY [[VMULSDrr]]
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; AVX: $xmm0 = COPY [[COPY4]]
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; AVX: RET 0, implicit $xmm0
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; AVX512F-LABEL: name: test_fmul_double
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; AVX512F: [[COPY:%[0-9]+]]:vr128x = COPY $xmm0
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; AVX512F: [[COPY1:%[0-9]+]]:fr64x = COPY [[COPY]]
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; AVX512F: [[COPY2:%[0-9]+]]:vr128x = COPY $xmm1
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; AVX512F: [[COPY3:%[0-9]+]]:fr64x = COPY [[COPY2]]
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; AVX512F: [[VMULSDZrr:%[0-9]+]]:fr64x = VMULSDZrr [[COPY1]], [[COPY3]]
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; AVX512F: [[COPY4:%[0-9]+]]:vr128x = COPY [[VMULSDZrr]]
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; AVX512F: $xmm0 = COPY [[COPY4]]
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; AVX512F: RET 0, implicit $xmm0
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; AVX512VL-LABEL: name: test_fmul_double
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; AVX512VL: [[COPY:%[0-9]+]]:vr128x = COPY $xmm0
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; AVX512VL: [[COPY1:%[0-9]+]]:fr64x = COPY [[COPY]]
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; AVX512VL: [[COPY2:%[0-9]+]]:vr128x = COPY $xmm1
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; AVX512VL: [[COPY3:%[0-9]+]]:fr64x = COPY [[COPY2]]
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; AVX512VL: [[VMULSDZrr:%[0-9]+]]:fr64x = VMULSDZrr [[COPY1]], [[COPY3]]
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; AVX512VL: [[COPY4:%[0-9]+]]:vr128x = COPY [[VMULSDZrr]]
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; AVX512VL: $xmm0 = COPY [[COPY4]]
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; AVX512VL: RET 0, implicit $xmm0
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%2:vecr(s128) = COPY $xmm0
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%0:vecr(s64) = G_TRUNC %2(s128)
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%3:vecr(s128) = COPY $xmm1
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%1:vecr(s64) = G_TRUNC %3(s128)
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%4:vecr(s64) = G_FMUL %0, %1
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%5:vecr(s128) = G_ANYEXT %4(s64)
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$xmm0 = COPY %5(s128)
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RET 0, implicit $xmm0
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...
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