forked from OSchip/llvm-project
27 lines
1.2 KiB
LLVM
27 lines
1.2 KiB
LLVM
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mtriple=amdgcn---amdgiz -mattr=+promote-alloca -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
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target datalayout = "A5"
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declare {}* @llvm.invariant.start.p5i8(i64, i8 addrspace(5)* nocapture) #0
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declare void @llvm.invariant.end.p5i8({}*, i64, i8 addrspace(5)* nocapture) #0
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declare i8 addrspace(5)* @llvm.invariant.group.barrier.p5i8(i8 addrspace(5)*) #1
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; GCN-LABEL: {{^}}use_invariant_promotable_lds:
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; GCN: buffer_load_dword
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; GCN: ds_write_b32
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define amdgpu_kernel void @use_invariant_promotable_lds(i32 addrspace(1)* %arg) #2 {
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bb:
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%tmp = alloca i32, align 4, addrspace(5)
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%tmp1 = bitcast i32 addrspace(5)* %tmp to i8 addrspace(5)*
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%tmp2 = getelementptr inbounds i32, i32 addrspace(1)* %arg, i64 1
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%tmp3 = load i32, i32 addrspace(1)* %tmp2
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store i32 %tmp3, i32 addrspace(5)* %tmp
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%tmp4 = call {}* @llvm.invariant.start.p5i8(i64 4, i8 addrspace(5)* %tmp1) #0
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call void @llvm.invariant.end.p5i8({}* %tmp4, i64 4, i8 addrspace(5)* %tmp1) #0
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%tmp5 = call i8 addrspace(5)* @llvm.invariant.group.barrier.p5i8(i8 addrspace(5)* %tmp1) #1
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ret void
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}
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attributes #0 = { argmemonly nounwind }
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attributes #1 = { nounwind readnone }
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attributes #2 = { nounwind }
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