llvm-project/llvm/test/CodeGen/AMDGPU/hazard-inlineasm.mir

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# RUN: llc -mcpu=gfx900 -march=amdgcn -verify-machineinstrs -run-pass post-RA-hazard-rec %s -o - | FileCheck %s
# If an INLINEASM statement is preceded by a vmem store of more than 8 bytes *and*
# the INLINEASM defs the vregs holding the data-to-be-stored by that preceding store,
# then the hazard recognizer should insert a s_nop in between them.
...
# GCN-LABEL: name: hazard-inlineasm
# CHECK: FLAT_STORE_DWORDX4
# CHECK-NEXT: S_NOP 0
# CHECK-NEXT: INLINEASM
---
name: hazard-inlineasm
body: |
bb.0:
FLAT_STORE_DWORDX4 %vgpr49_vgpr50, %vgpr26_vgpr27_vgpr28_vgpr29, 0, 0, 0, implicit %exec, implicit %flat_scr
INLINEASM $"v_mad_u64_u32 $0, $1, $2, $3, $4", 0, 2621450, def %vgpr26_vgpr27, 2818058, def dead %sgpr14_sgpr15, 589833, %sgpr12, 327689, killed %vgpr51, 2621449, %vgpr46_vgpr47
S_ENDPGM
...