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AArch64
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[ARM][AArch64] Adding Neoverse N2 CPU support
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2020-11-25 11:42:54 +00:00 |
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AMDGPU
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[AMDGPU][MC] Improved diagnostic messages
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2020-11-23 16:15:05 +03:00 |
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ARM
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[ARMAttributeParser] Correctly parse and print Tag_THUMB_ISA_use=3
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2020-11-28 12:28:22 -08:00 |
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AVR
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[AVRInstPrinter] printOperand: support llvm-objdump --print-imm-hex
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2020-07-12 08:14:52 -07:00 |
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AsmParser
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[MC/AsmParser] Fix use of Arm calling convention in target-agnostic test
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2020-11-24 22:56:27 +00:00 |
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BPF
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[test] llvm/test/: change llvm-objdump single-dash long options to double-dash options
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2020-03-15 17:46:23 -07:00 |
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COFF
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[test][MC] Use %python in llvm/test/MC/COFF/bigobj.py
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2020-10-07 14:03:28 -04:00 |
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Disassembler
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[ARM][AArch64] Adding Neoverse N2 CPU support
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2020-11-25 11:42:54 +00:00 |
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ELF
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[MC] Copy visibility for .symver created symbols
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2020-11-29 16:51:48 -08:00 |
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Hexagon
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[llvm-readobj] Update tests because of changes in llvm-readobj behavior
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2020-07-20 10:39:04 +01:00 |
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Lanai
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MSP430
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[llvm-readobj] Update tests because of changes in llvm-readobj behavior
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2020-07-20 10:39:04 +01:00 |
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MachO
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llvm-dwarfdump: Dump address forms in their encoded length rather than always in 64 bits
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2020-10-04 15:48:57 -07:00 |
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Mips
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[MC][mips] Remove unused check prefixes. NFC
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2020-11-13 14:31:13 +03:00 |
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PowerPC
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[PowerPC] Allow a '%' prefix for registers in CFI directives
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2020-11-19 18:19:51 -08:00 |
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RISCV
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[RISCV] Use register class VR for V instruction operands directly.
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2020-11-19 05:59:46 +08:00 |
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Sparc
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[llvm-readobj] Update tests because of changes in llvm-readobj behavior
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2020-07-20 10:39:04 +01:00 |
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SystemZ
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[SystemZAsmParser] Treat VR128 separately in ParseDirectiveInsn().
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2020-10-06 14:42:40 +02:00 |
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VE
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[VE] Add missing BCR format
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2020-10-29 23:30:49 +09:00 |
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WebAssembly
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[MC][WebAssembly] Only emit indirect function table import if needed
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2020-11-25 08:38:43 -08:00 |
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X86
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[AsmParser] Add source location to all errors related to .cfi directives
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2020-11-11 17:00:07 +00:00 |
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