forked from OSchip/llvm-project
98 lines
3.1 KiB
YAML
98 lines
3.1 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect -regbankselect-fast -verify-machineinstrs -o - %s | FileCheck %s
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# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect -regbankselect-greedy -verify-machineinstrs -o - %s | FileCheck %s
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---
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name: zextload_constant_i8_to_i32_uniform
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legalized: true
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body: |
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bb.0:
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liveins: $sgpr0_sgpr1
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; CHECK-LABEL: name: zextload_constant_i8_to_i32_uniform
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; CHECK: [[COPY:%[0-9]+]]:sgpr(p4) = COPY $sgpr0_sgpr1
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; CHECK: [[COPY1:%[0-9]+]]:vgpr(p4) = COPY [[COPY]](p4)
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; CHECK: [[ZEXTLOAD:%[0-9]+]]:vgpr(s32) = G_ZEXTLOAD [[COPY1]](p4) :: (load 1, addrspace 4)
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%0:_(p4) = COPY $sgpr0_sgpr1
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%1:_(s32) = G_ZEXTLOAD %0 :: (load 1, addrspace 4, align 1)
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...
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---
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name: zextload_global_i8_to_i32_uniform
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legalized: true
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body: |
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bb.0:
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liveins: $sgpr0_sgpr1
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; CHECK-LABEL: name: zextload_global_i8_to_i32_uniform
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; CHECK: [[COPY:%[0-9]+]]:sgpr(p4) = COPY $sgpr0_sgpr1
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; CHECK: [[COPY1:%[0-9]+]]:vgpr(p4) = COPY [[COPY]](p4)
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; CHECK: [[ZEXTLOAD:%[0-9]+]]:vgpr(s32) = G_ZEXTLOAD [[COPY1]](p4) :: (load 1, addrspace 1)
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%0:_(p4) = COPY $sgpr0_sgpr1
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%1:_(s32) = G_ZEXTLOAD %0 :: (load 1, addrspace 1, align 1)
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...
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---
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name: zextload_constant_i16_to_i32_uniform
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legalized: true
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body: |
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bb.0:
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liveins: $sgpr0_sgpr1
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; CHECK-LABEL: name: zextload_constant_i16_to_i32_uniform
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; CHECK: [[COPY:%[0-9]+]]:sgpr(p4) = COPY $sgpr0_sgpr1
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; CHECK: [[COPY1:%[0-9]+]]:vgpr(p4) = COPY [[COPY]](p4)
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; CHECK: [[ZEXTLOAD:%[0-9]+]]:vgpr(s32) = G_ZEXTLOAD [[COPY1]](p4) :: (load 2, addrspace 4)
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%0:_(p4) = COPY $sgpr0_sgpr1
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%1:_(s32) = G_ZEXTLOAD %0 :: (load 2, addrspace 4, align 2)
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...
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---
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name: zextload_global_i16_to_i32_uniform
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legalized: true
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body: |
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bb.0:
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liveins: $sgpr0_sgpr1
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; CHECK-LABEL: name: zextload_global_i16_to_i32_uniform
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; CHECK: [[COPY:%[0-9]+]]:sgpr(p4) = COPY $sgpr0_sgpr1
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; CHECK: [[COPY1:%[0-9]+]]:vgpr(p4) = COPY [[COPY]](p4)
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; CHECK: [[ZEXTLOAD:%[0-9]+]]:vgpr(s32) = G_ZEXTLOAD [[COPY1]](p4) :: (load 2, addrspace 1)
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%0:_(p4) = COPY $sgpr0_sgpr1
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%1:_(s32) = G_ZEXTLOAD %0 :: (load 2, addrspace 1, align 2)
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...
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---
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name: zextload_local_i8_to_i32_uniform
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legalized: true
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body: |
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bb.0:
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liveins: $sgpr0
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; CHECK-LABEL: name: zextload_local_i8_to_i32_uniform
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; CHECK: [[COPY:%[0-9]+]]:sgpr(p3) = COPY $sgpr0
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; CHECK: [[COPY1:%[0-9]+]]:vgpr(p3) = COPY [[COPY]](p3)
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; CHECK: [[ZEXTLOAD:%[0-9]+]]:vgpr(s32) = G_ZEXTLOAD [[COPY1]](p3) :: (load 1, addrspace 3)
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%0:_(p3) = COPY $sgpr0
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%1:_(s32) = G_ZEXTLOAD %0 :: (load 1, addrspace 3, align 1)
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...
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---
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name: zextload_local_i16_to_i32_uniform
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legalized: true
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body: |
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bb.0:
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liveins: $sgpr0
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; CHECK-LABEL: name: zextload_local_i16_to_i32_uniform
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; CHECK: [[COPY:%[0-9]+]]:sgpr(p3) = COPY $sgpr0
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; CHECK: [[COPY1:%[0-9]+]]:vgpr(p3) = COPY [[COPY]](p3)
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; CHECK: [[ZEXTLOAD:%[0-9]+]]:vgpr(s32) = G_ZEXTLOAD [[COPY1]](p3) :: (load 2, addrspace 3)
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%0:_(p3) = COPY $sgpr0
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%1:_(s32) = G_ZEXTLOAD %0 :: (load 2, addrspace 3, align 2)
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...
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