forked from OSchip/llvm-project
311 lines
11 KiB
YAML
311 lines
11 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -march=amdgcn -mcpu=gfx908 -run-pass=regbankselect -regbankselect-fast -verify-machineinstrs -o - %s | FileCheck %s
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# RUN: llc -march=amdgcn -mcpu=gfx908 -run-pass=regbankselect -regbankselect-greedy -verify-machineinstrs -o - %s | FileCheck %s
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---
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name: build_vector_v2s32_ss
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legalized: true
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body: |
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bb.0:
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liveins: $sgpr0, $sgpr1
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; CHECK-LABEL: name: build_vector_v2s32_ss
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; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
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; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
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; CHECK: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<2 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32)
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%0:_(s32) = COPY $sgpr0
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%1:_(s32) = COPY $sgpr1
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%2:_(<2 x s32>) = G_BUILD_VECTOR %0, %1
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...
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---
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name: build_vector_v2s32_sv
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legalized: true
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body: |
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bb.0:
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liveins: $sgpr0, $vgpr0
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; CHECK-LABEL: name: build_vector_v2s32_sv
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; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
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; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
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; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)
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; CHECK: [[BUILD_VECTOR:%[0-9]+]]:vgpr(<2 x s32>) = G_BUILD_VECTOR [[COPY2]](s32), [[COPY1]](s32)
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%0:_(s32) = COPY $sgpr0
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%1:_(s32) = COPY $vgpr0
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%2:_(<2 x s32>) = G_BUILD_VECTOR %0, %1
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...
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---
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name: build_vector_v2s32_vs
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legalized: true
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body: |
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bb.0:
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liveins: $vgpr0, $sgpr0
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; CHECK-LABEL: name: build_vector_v2s32_vs
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; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
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; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
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; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
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; CHECK: [[BUILD_VECTOR:%[0-9]+]]:vgpr(<2 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY2]](s32)
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%0:_(s32) = COPY $vgpr0
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%1:_(s32) = COPY $sgpr0
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%2:_(<2 x s32>) = G_BUILD_VECTOR %0, %1
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...
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---
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name: build_vector_v2s32_vv
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legalized: true
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body: |
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bb.0:
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liveins: $vgpr0, $vgpr1
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; CHECK-LABEL: name: build_vector_v2s32_vv
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; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
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; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
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; CHECK: [[BUILD_VECTOR:%[0-9]+]]:vgpr(<2 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32)
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%0:_(s32) = COPY $vgpr0
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%1:_(s32) = COPY $vgpr1
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%2:_(<2 x s32>) = G_BUILD_VECTOR %0, %1
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...
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---
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name: build_vector_v2s32_aa
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tracksRegLiveness: true
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legalized: true
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body: |
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bb.0:
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liveins: $agpr0, $agpr1
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; CHECK-LABEL: name: build_vector_v2s32_aa
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; CHECK: liveins: $agpr0, $agpr1
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; CHECK: [[COPY:%[0-9]+]]:agpr(s32) = COPY $agpr0
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; CHECK: [[COPY1:%[0-9]+]]:agpr(s32) = COPY $agpr1
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; CHECK: [[BUILD_VECTOR:%[0-9]+]]:agpr(<2 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32)
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; CHECK: S_ENDPGM 0, implicit [[BUILD_VECTOR]](<2 x s32>)
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%0:_(s32) = COPY $agpr0
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%1:_(s32) = COPY $agpr1
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%2:_(<2 x s32>) = G_BUILD_VECTOR %0, %1
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S_ENDPGM 0, implicit %2
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...
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---
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name: build_vector_v2s32_va
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tracksRegLiveness: true
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legalized: true
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body: |
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bb.0:
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liveins: $vgpr0, $agpr0
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; CHECK-LABEL: name: build_vector_v2s32_va
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; CHECK: liveins: $vgpr0, $agpr0
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; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
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; CHECK: [[COPY1:%[0-9]+]]:agpr(s32) = COPY $agpr0
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; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
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; CHECK: [[BUILD_VECTOR:%[0-9]+]]:vgpr(<2 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY2]](s32)
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; CHECK: S_ENDPGM 0, implicit [[BUILD_VECTOR]](<2 x s32>)
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%0:_(s32) = COPY $vgpr0
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%1:_(s32) = COPY $agpr0
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%2:_(<2 x s32>) = G_BUILD_VECTOR %0, %1
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S_ENDPGM 0, implicit %2
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...
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---
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name: build_vector_v2s32_av
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tracksRegLiveness: true
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legalized: true
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body: |
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bb.0:
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liveins: $vgpr0, $agpr0
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; CHECK-LABEL: name: build_vector_v2s32_av
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; CHECK: liveins: $vgpr0, $agpr0
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; CHECK: [[COPY:%[0-9]+]]:agpr(s32) = COPY $agpr0
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; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
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; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)
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; CHECK: [[BUILD_VECTOR:%[0-9]+]]:vgpr(<2 x s32>) = G_BUILD_VECTOR [[COPY2]](s32), [[COPY1]](s32)
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; CHECK: S_ENDPGM 0, implicit [[BUILD_VECTOR]](<2 x s32>)
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%0:_(s32) = COPY $agpr0
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%1:_(s32) = COPY $vgpr0
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%2:_(<2 x s32>) = G_BUILD_VECTOR %0, %1
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S_ENDPGM 0, implicit %2
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...
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---
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name: build_vector_v2s32_sa
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tracksRegLiveness: true
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legalized: true
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body: |
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bb.0:
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liveins: $sgpr0, $agpr0
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; CHECK-LABEL: name: build_vector_v2s32_sa
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; CHECK: liveins: $sgpr0, $agpr0
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; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
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; CHECK: [[COPY1:%[0-9]+]]:agpr(s32) = COPY $agpr0
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; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)
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; CHECK: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
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; CHECK: [[BUILD_VECTOR:%[0-9]+]]:vgpr(<2 x s32>) = G_BUILD_VECTOR [[COPY2]](s32), [[COPY3]](s32)
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; CHECK: S_ENDPGM 0, implicit [[BUILD_VECTOR]](<2 x s32>)
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%0:_(s32) = COPY $sgpr0
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%1:_(s32) = COPY $agpr0
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%2:_(<2 x s32>) = G_BUILD_VECTOR %0, %1
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S_ENDPGM 0, implicit %2
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...
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---
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name: build_vector_v2s32_as
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tracksRegLiveness: true
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legalized: true
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body: |
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bb.0:
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liveins: $sgpr0, $agpr0
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; CHECK-LABEL: name: build_vector_v2s32_as
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; CHECK: liveins: $sgpr0, $agpr0
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; CHECK: [[COPY:%[0-9]+]]:agpr(s32) = COPY $agpr0
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; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
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; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)
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; CHECK: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
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; CHECK: [[BUILD_VECTOR:%[0-9]+]]:vgpr(<2 x s32>) = G_BUILD_VECTOR [[COPY2]](s32), [[COPY3]](s32)
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; CHECK: S_ENDPGM 0, implicit [[BUILD_VECTOR]](<2 x s32>)
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%0:_(s32) = COPY $agpr0
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%1:_(s32) = COPY $sgpr0
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%2:_(<2 x s32>) = G_BUILD_VECTOR %0, %1
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S_ENDPGM 0, implicit %2
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...
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---
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name: build_vector_v3s32_aaa
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tracksRegLiveness: true
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legalized: true
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body: |
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bb.0:
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liveins: $agpr0, $agpr1, $agpr2
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; CHECK-LABEL: name: build_vector_v3s32_aaa
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; CHECK: liveins: $agpr0, $agpr1, $agpr2
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; CHECK: [[COPY:%[0-9]+]]:agpr(s32) = COPY $agpr0
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; CHECK: [[COPY1:%[0-9]+]]:agpr(s32) = COPY $agpr1
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; CHECK: [[COPY2:%[0-9]+]]:agpr(s32) = COPY $agpr2
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; CHECK: [[BUILD_VECTOR:%[0-9]+]]:agpr(<3 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32)
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; CHECK: S_ENDPGM 0, implicit [[BUILD_VECTOR]](<3 x s32>)
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%0:_(s32) = COPY $agpr0
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%1:_(s32) = COPY $agpr1
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%2:_(s32) = COPY $agpr2
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%3:_(<3 x s32>) = G_BUILD_VECTOR %0, %1, %2
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S_ENDPGM 0, implicit %3
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...
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---
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name: build_vector_v4s32_aaaa
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tracksRegLiveness: true
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legalized: true
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body: |
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bb.0:
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liveins: $agpr0, $agpr1, $agpr2
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; CHECK-LABEL: name: build_vector_v4s32_aaaa
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; CHECK: liveins: $agpr0, $agpr1, $agpr2
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; CHECK: [[COPY:%[0-9]+]]:agpr(s32) = COPY $agpr0
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; CHECK: [[COPY1:%[0-9]+]]:agpr(s32) = COPY $agpr1
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; CHECK: [[COPY2:%[0-9]+]]:agpr(s32) = COPY $agpr2
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; CHECK: [[COPY3:%[0-9]+]]:agpr(s32) = COPY $agpr2
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; CHECK: [[BUILD_VECTOR:%[0-9]+]]:agpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32)
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; CHECK: S_ENDPGM 0, implicit [[BUILD_VECTOR]](<4 x s32>)
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%0:_(s32) = COPY $agpr0
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%1:_(s32) = COPY $agpr1
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%2:_(s32) = COPY $agpr2
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%3:_(s32) = COPY $agpr2
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%4:_(<4 x s32>) = G_BUILD_VECTOR %0, %1, %2, %3
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S_ENDPGM 0, implicit %4
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...
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---
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name: build_vector_v8s32_aaaaaaaa
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tracksRegLiveness: true
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legalized: true
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body: |
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bb.0:
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liveins: $agpr0, $agpr1, $agpr2, $agpr3, $agpr4, $agpr5, $agpr6, $agpr7
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; CHECK-LABEL: name: build_vector_v8s32_aaaaaaaa
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; CHECK: liveins: $agpr0, $agpr1, $agpr2, $agpr3, $agpr4, $agpr5, $agpr6, $agpr7
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; CHECK: [[COPY:%[0-9]+]]:agpr(s32) = COPY $agpr0
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; CHECK: [[COPY1:%[0-9]+]]:agpr(s32) = COPY $agpr1
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; CHECK: [[COPY2:%[0-9]+]]:agpr(s32) = COPY $agpr2
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; CHECK: [[COPY3:%[0-9]+]]:agpr(s32) = COPY $agpr3
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; CHECK: [[COPY4:%[0-9]+]]:agpr(s32) = COPY $agpr4
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; CHECK: [[COPY5:%[0-9]+]]:agpr(s32) = COPY $agpr5
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; CHECK: [[COPY6:%[0-9]+]]:agpr(s32) = COPY $agpr6
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; CHECK: [[COPY7:%[0-9]+]]:agpr(s32) = COPY $agpr7
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; CHECK: [[BUILD_VECTOR:%[0-9]+]]:agpr(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
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; CHECK: S_ENDPGM 0, implicit [[BUILD_VECTOR]](<8 x s32>)
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%0:_(s32) = COPY $agpr0
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%1:_(s32) = COPY $agpr1
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%2:_(s32) = COPY $agpr2
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%3:_(s32) = COPY $agpr3
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%4:_(s32) = COPY $agpr4
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%5:_(s32) = COPY $agpr5
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%6:_(s32) = COPY $agpr6
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%7:_(s32) = COPY $agpr7
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%8:_(<8 x s32>) = G_BUILD_VECTOR %0, %1, %2, %3, %4, %5, %6, %7
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S_ENDPGM 0, implicit %8
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...
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---
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name: build_vector_v16s32_aaaaaaaaaaaaaaaa
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tracksRegLiveness: true
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legalized: true
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body: |
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bb.0:
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liveins: $agpr0, $agpr1, $agpr2, $agpr3, $agpr4, $agpr5, $agpr6, $agpr7, $agpr8, $agpr9, $agpr10, $agpr11, $agpr12, $agpr13, $agpr14, $agpr15
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; CHECK-LABEL: name: build_vector_v16s32_aaaaaaaaaaaaaaaa
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; CHECK: liveins: $agpr0, $agpr1, $agpr2, $agpr3, $agpr4, $agpr5, $agpr6, $agpr7, $agpr8, $agpr9, $agpr10, $agpr11, $agpr12, $agpr13, $agpr14, $agpr15
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; CHECK: [[COPY:%[0-9]+]]:agpr(s32) = COPY $agpr0
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; CHECK: [[COPY1:%[0-9]+]]:agpr(s32) = COPY $agpr1
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; CHECK: [[COPY2:%[0-9]+]]:agpr(s32) = COPY $agpr2
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; CHECK: [[COPY3:%[0-9]+]]:agpr(s32) = COPY $agpr3
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; CHECK: [[COPY4:%[0-9]+]]:agpr(s32) = COPY $agpr4
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; CHECK: [[COPY5:%[0-9]+]]:agpr(s32) = COPY $agpr5
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; CHECK: [[COPY6:%[0-9]+]]:agpr(s32) = COPY $agpr6
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; CHECK: [[COPY7:%[0-9]+]]:agpr(s32) = COPY $agpr7
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; CHECK: [[COPY8:%[0-9]+]]:agpr(s32) = COPY $agpr8
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; CHECK: [[COPY9:%[0-9]+]]:agpr(s32) = COPY $agpr9
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; CHECK: [[COPY10:%[0-9]+]]:agpr(s32) = COPY $agpr10
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; CHECK: [[COPY11:%[0-9]+]]:agpr(s32) = COPY $agpr11
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; CHECK: [[COPY12:%[0-9]+]]:agpr(s32) = COPY $agpr12
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; CHECK: [[COPY13:%[0-9]+]]:agpr(s32) = COPY $agpr13
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; CHECK: [[COPY14:%[0-9]+]]:agpr(s32) = COPY $agpr14
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; CHECK: [[COPY15:%[0-9]+]]:agpr(s32) = COPY $agpr15
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; CHECK: [[BUILD_VECTOR:%[0-9]+]]:agpr(<16 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32), [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32), [[COPY12]](s32), [[COPY13]](s32), [[COPY14]](s32), [[COPY15]](s32)
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; CHECK: S_ENDPGM 0, implicit [[BUILD_VECTOR]](<16 x s32>)
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%0:_(s32) = COPY $agpr0
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%1:_(s32) = COPY $agpr1
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%2:_(s32) = COPY $agpr2
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%3:_(s32) = COPY $agpr3
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%4:_(s32) = COPY $agpr4
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%5:_(s32) = COPY $agpr5
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%6:_(s32) = COPY $agpr6
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%7:_(s32) = COPY $agpr7
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%8:_(s32) = COPY $agpr8
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%9:_(s32) = COPY $agpr9
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%10:_(s32) = COPY $agpr10
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%11:_(s32) = COPY $agpr11
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%12:_(s32) = COPY $agpr12
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%13:_(s32) = COPY $agpr13
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%14:_(s32) = COPY $agpr14
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%15:_(s32) = COPY $agpr15
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%16:_(<16 x s32>) = G_BUILD_VECTOR %0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15
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S_ENDPGM 0, implicit %16
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...
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