forked from OSchip/llvm-project
118 lines
4.5 KiB
YAML
118 lines
4.5 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -O0 -run-pass=legalizer -global-isel-abort=0 %s -o - | FileCheck %s
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---
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name: test_ssube_s32
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body: |
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bb.0:
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liveins: $vgpr0, $vgpr1, $vgpr2
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; CHECK-LABEL: name: test_ssube_s32
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; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
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; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
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; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2
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; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
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; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]]
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; CHECK: [[SSUBE:%[0-9]+]]:_(s32), [[SSUBE1:%[0-9]+]]:_(s1) = G_SSUBE [[COPY]], [[COPY1]], [[ICMP]]
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; CHECK: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[SSUBE1]](s1)
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; CHECK: $vgpr0 = COPY [[SSUBE]](s32)
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; CHECK: $vgpr1 = COPY [[ZEXT]](s32)
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%0:_(s32) = COPY $vgpr0
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%1:_(s32) = COPY $vgpr1
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%2:_(s32) = COPY $vgpr2
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%3:_(s32) = G_CONSTANT i32 0
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%4:_(s1) = G_ICMP intpred(eq), %2, %3
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%5:_(s32), %6:_(s1) = G_SSUBE %0, %1, %4
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%7:_(s32) = G_ZEXT %6
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$vgpr0 = COPY %5
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$vgpr1 = COPY %7
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...
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---
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name: test_ssube_v2s32
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body: |
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bb.0:
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liveins: $vgpr0_vgpr1, $vgpr2_vgpr3, $vgpr4_vgpr5
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; CHECK-LABEL: name: test_ssube_v2s32
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; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
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; CHECK: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr2_vgpr3
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; CHECK: [[COPY2:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr4_vgpr5
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; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
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; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[C]](s32), [[C]](s32)
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; CHECK: [[ICMP:%[0-9]+]]:_(<2 x s1>) = G_ICMP intpred(eq), [[COPY2]](<2 x s32>), [[BUILD_VECTOR]]
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; CHECK: [[SSUBE:%[0-9]+]]:_(<2 x s32>), [[SSUBE1:%[0-9]+]]:_(<2 x s1>) = G_SSUBE [[COPY]], [[COPY1]], [[ICMP]]
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; CHECK: [[ZEXT:%[0-9]+]]:_(<2 x s32>) = G_ZEXT [[SSUBE1]](<2 x s1>)
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; CHECK: $vgpr0_vgpr1 = COPY [[SSUBE]](<2 x s32>)
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; CHECK: $vgpr2_vgpr3 = COPY [[ZEXT]](<2 x s32>)
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%0:_(<2 x s32>) = COPY $vgpr0_vgpr1
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%1:_(<2 x s32>) = COPY $vgpr2_vgpr3
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%2:_(<2 x s32>) = COPY $vgpr4_vgpr5
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%3:_(s32) = G_CONSTANT i32 0
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%4:_(<2 x s32>) = G_BUILD_VECTOR %3, %3
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%5:_(<2 x s1>) = G_ICMP intpred(eq), %2, %4
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%6:_(<2 x s32>), %7:_(<2 x s1>) = G_SSUBE %0, %1, %5
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%8:_(<2 x s32>) = G_ZEXT %7
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$vgpr0_vgpr1 = COPY %6
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$vgpr2_vgpr3 = COPY %8
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...
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---
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name: test_ssube_s16
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body: |
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bb.0:
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liveins: $vgpr0, $vgpr1, $vgpr2
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; CHECK-LABEL: name: test_ssube_s16
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; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
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; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
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; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2
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; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
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; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]]
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; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
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; CHECK: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
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; CHECK: [[SSUBE:%[0-9]+]]:_(s16), [[SSUBE1:%[0-9]+]]:_(s1) = G_SSUBE [[TRUNC1]], [[SSUBE]], [[ICMP]]
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; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SSUBE]](s16)
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; CHECK: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[SSUBE1]](s1)
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; CHECK: $vgpr0 = COPY [[ANYEXT]](s32)
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; CHECK: $vgpr1 = COPY [[ZEXT]](s32)
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%0:_(s32) = COPY $vgpr0
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%1:_(s32) = COPY $vgpr1
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%2:_(s32) = COPY $vgpr2
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%3:_(s32) = G_CONSTANT i32 0
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%4:_(s1) = G_ICMP intpred(eq), %2, %3
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%5:_(s16) = G_TRUNC %0
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%6:_(s16) = G_TRUNC %1
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%7:_(s16), %8:_(s1) = G_SSUBE %6, %7, %4
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%9:_(s32) = G_ANYEXT %7
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%10:_(s32) = G_ZEXT %8
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$vgpr0 = COPY %9
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$vgpr1 = COPY %10
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...
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---
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name: test_ssube_s64
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body: |
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bb.0:
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liveins: $vgpr0_vgpr1, $vgpr2_vgpr3, $vgpr4
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; CHECK-LABEL: name: test_ssube_s64
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; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
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; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr2_vgpr3
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; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr4
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; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
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; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]]
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; CHECK: [[SSUBE:%[0-9]+]]:_(s64), [[SSUBE1:%[0-9]+]]:_(s1) = G_SSUBE [[COPY]], [[COPY1]], [[ICMP]]
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; CHECK: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[SSUBE1]](s1)
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; CHECK: $vgpr0_vgpr1 = COPY [[SSUBE]](s64)
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; CHECK: $vgpr2 = COPY [[ZEXT]](s32)
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%0:_(s64) = COPY $vgpr0_vgpr1
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%1:_(s64) = COPY $vgpr2_vgpr3
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%2:_(s32) = COPY $vgpr4
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%3:_(s32) = G_CONSTANT i32 0
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%4:_(s1) = G_ICMP intpred(eq), %2, %3
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%5:_(s64), %6:_(s1) = G_SSUBE %0, %1, %4
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%7:_(s32) = G_ZEXT %6
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$vgpr0_vgpr1 = COPY %5
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$vgpr2 = COPY %7
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...
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