forked from OSchip/llvm-project
164 lines
7.0 KiB
YAML
164 lines
7.0 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=bonaire -O0 -run-pass=legalizer %s -o - | FileCheck -check-prefix=CI %s
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---
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name: test_sextload_constant32bit_s64_s32_align4
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body: |
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bb.0:
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liveins: $sgpr0
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; CI-LABEL: name: test_sextload_constant32bit_s64_s32_align4
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; CI: [[COPY:%[0-9]+]]:_(p6) = COPY $sgpr0
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; CI: [[C:%[0-9]+]]:_(p6) = G_CONSTANT i32 0
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; CI: [[MV:%[0-9]+]]:_(p4) = G_MERGE_VALUES [[COPY]](p6), [[C]](p6)
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; CI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[MV]](p4) :: (load 4, addrspace 6)
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; CI: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[LOAD]](s32)
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; CI: $vgpr0_vgpr1 = COPY [[SEXT]](s64)
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%0:_(p6) = COPY $sgpr0
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%1:_(s64) = G_SEXTLOAD %0 :: (load 4, align 4, addrspace 6)
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$vgpr0_vgpr1 = COPY %1
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...
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---
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name: test_sextload_constant32bit_s64_s32_align2
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body: |
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bb.0:
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liveins: $sgpr0
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; CI-LABEL: name: test_sextload_constant32bit_s64_s32_align2
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; CI: [[COPY:%[0-9]+]]:_(p6) = COPY $sgpr0
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; CI: [[C:%[0-9]+]]:_(p6) = G_CONSTANT i32 0
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; CI: [[MV:%[0-9]+]]:_(p4) = G_MERGE_VALUES [[COPY]](p6), [[C]](p6)
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; CI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[MV]](p4) :: (load 2, addrspace 6)
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; CI: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
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; CI: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[MV]], [[C1]](s64)
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; CI: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p4) :: (load 2 + 2, addrspace 6)
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; CI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
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; CI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
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; CI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C2]]
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; CI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
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; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C2]]
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; CI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
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; CI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C3]](s32)
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; CI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
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; CI: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[OR]](s32)
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; CI: $vgpr0_vgpr1 = COPY [[SEXT]](s64)
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%0:_(p6) = COPY $sgpr0
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%1:_(s64) = G_SEXTLOAD %0 :: (load 4, align 2, addrspace 6)
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$vgpr0_vgpr1 = COPY %1
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...
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---
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name: test_sextload_constant32bit_s64_s32_align1
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body: |
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bb.0:
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liveins: $sgpr0
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; CI-LABEL: name: test_sextload_constant32bit_s64_s32_align1
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; CI: [[COPY:%[0-9]+]]:_(p6) = COPY $sgpr0
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; CI: [[C:%[0-9]+]]:_(p6) = G_CONSTANT i32 0
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; CI: [[MV:%[0-9]+]]:_(p4) = G_MERGE_VALUES [[COPY]](p6), [[C]](p6)
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; CI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[MV]](p4) :: (load 1, addrspace 6)
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; CI: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
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; CI: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[MV]], [[C1]](s64)
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; CI: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p4) :: (load 1 + 1, addrspace 6)
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; CI: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
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; CI: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[MV]], [[C2]](s64)
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; CI: [[LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD1]](p4) :: (load 1 + 2, addrspace 6)
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; CI: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 3
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; CI: [[PTR_ADD2:%[0-9]+]]:_(p4) = G_PTR_ADD [[MV]], [[C3]](s64)
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; CI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p4) :: (load 1 + 3, addrspace 6)
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; CI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
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; CI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
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; CI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C4]]
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; CI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
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; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C4]]
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; CI: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
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; CI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C5]](s32)
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; CI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
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; CI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
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; CI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C4]]
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; CI: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
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; CI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C6]](s32)
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; CI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
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; CI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
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; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C4]]
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; CI: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
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; CI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C7]](s32)
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; CI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
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; CI: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[OR2]](s32)
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; CI: $vgpr0_vgpr1 = COPY [[SEXT]](s64)
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%0:_(p6) = COPY $sgpr0
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%1:_(s64) = G_SEXTLOAD %0 :: (load 4, align 1, addrspace 6)
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$vgpr0_vgpr1 = COPY %1
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...
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---
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name: test_sextload_constant32bit_s32_s8_align1
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body: |
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bb.0:
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liveins: $sgpr0
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; CI-LABEL: name: test_sextload_constant32bit_s32_s8_align1
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; CI: [[COPY:%[0-9]+]]:_(p6) = COPY $sgpr0
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; CI: [[C:%[0-9]+]]:_(p6) = G_CONSTANT i32 0
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; CI: [[MV:%[0-9]+]]:_(p4) = G_MERGE_VALUES [[COPY]](p6), [[C]](p6)
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; CI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[MV]](p4) :: (load 1, addrspace 6)
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; CI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
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; CI: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY1]], 8
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; CI: $vgpr0 = COPY [[SEXT_INREG]](s32)
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%0:_(p6) = COPY $sgpr0
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%1:_(s32) = G_SEXTLOAD %0 :: (load 1, align 1, addrspace 6)
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$vgpr0 = COPY %1
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...
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---
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name: test_sextload_constant32bit_s32_s16_align2
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body: |
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bb.0:
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liveins: $sgpr0
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; CI-LABEL: name: test_sextload_constant32bit_s32_s16_align2
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; CI: [[COPY:%[0-9]+]]:_(p6) = COPY $sgpr0
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; CI: [[C:%[0-9]+]]:_(p6) = G_CONSTANT i32 0
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; CI: [[MV:%[0-9]+]]:_(p4) = G_MERGE_VALUES [[COPY]](p6), [[C]](p6)
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; CI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[MV]](p4) :: (load 2, addrspace 6)
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; CI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
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; CI: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY1]], 16
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; CI: $vgpr0 = COPY [[SEXT_INREG]](s32)
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%0:_(p6) = COPY $sgpr0
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%1:_(s32) = G_SEXTLOAD %0 :: (load 2, align 2, addrspace 6)
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$vgpr0 = COPY %1
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...
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---
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name: test_sextload_constant32bit_s32_s16_align1
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body: |
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bb.0:
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liveins: $sgpr0
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; CI-LABEL: name: test_sextload_constant32bit_s32_s16_align1
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; CI: [[COPY:%[0-9]+]]:_(p6) = COPY $sgpr0
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; CI: [[C:%[0-9]+]]:_(p6) = G_CONSTANT i32 0
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; CI: [[MV:%[0-9]+]]:_(p4) = G_MERGE_VALUES [[COPY]](p6), [[C]](p6)
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; CI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[MV]](p4) :: (load 1, addrspace 6)
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; CI: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
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; CI: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[MV]], [[C1]](s64)
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; CI: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p4) :: (load 1 + 1, addrspace 6)
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; CI: [[C2:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
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; CI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD]](s32)
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; CI: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C2]]
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; CI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
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; CI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
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; CI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
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; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C4]]
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; CI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C3]](s32)
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; CI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SHL]](s32)
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; CI: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[TRUNC1]]
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; CI: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[OR]](s16)
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; CI: $vgpr0 = COPY [[SEXT]](s32)
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%0:_(p6) = COPY $sgpr0
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%1:_(s32) = G_SEXTLOAD %0 :: (load 2, align 1, addrspace 6)
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$vgpr0 = COPY %1
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...
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