forked from OSchip/llvm-project
83 lines
2.1 KiB
YAML
83 lines
2.1 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -march=amdgcn -mcpu=hawaii -run-pass=instruction-select -global-isel-abort=0 -verify-machineinstrs -o - %s | FileCheck %s
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---
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name: fceil_s32_vv
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $vgpr0
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; CHECK-LABEL: name: fceil_s32_vv
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; CHECK: liveins: $vgpr0
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; CHECK: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; CHECK: %1:vgpr_32 = nofpexcept V_CEIL_F32_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
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; CHECK: $vgpr0 = COPY %1
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%0:vgpr(s32) = COPY $vgpr0
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%1:vgpr(s32) = G_FCEIL %0
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$vgpr0 = COPY %1
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...
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---
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name: fceil_s32_vs
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $sgpr0
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; CHECK-LABEL: name: fceil_s32_vs
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; CHECK: liveins: $sgpr0
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; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
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; CHECK: %1:vgpr_32 = nofpexcept V_CEIL_F32_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
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; CHECK: $vgpr0 = COPY %1
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%0:sgpr(s32) = COPY $sgpr0
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%1:vgpr(s32) = G_FCEIL %0
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$vgpr0 = COPY %1
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...
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---
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name: fceil_s64_sv
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $sgpr0_sgpr1
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; CHECK-LABEL: name: fceil_s64_sv
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; CHECK: liveins: $sgpr0_sgpr1
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; CHECK: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
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; CHECK: %1:vreg_64 = nofpexcept V_CEIL_F64_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
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; CHECK: $vgpr0_vgpr1 = COPY %1
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%0:sgpr(s64) = COPY $sgpr0_sgpr1
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%1:vgpr(s64) = G_FCEIL %0
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$vgpr0_vgpr1 = COPY %1
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...
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---
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name: fceil_s64_vv
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $vgpr0_vgpr1
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; CHECK-LABEL: name: fceil_s64_vv
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; CHECK: liveins: $vgpr0_vgpr1
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; CHECK: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
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; CHECK: %1:vreg_64 = nofpexcept V_CEIL_F64_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
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; CHECK: $vgpr0_vgpr1 = COPY %1
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%0:vgpr(s64) = COPY $vgpr0_vgpr1
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%1:vgpr(s64) = G_FCEIL %0
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$vgpr0_vgpr1 = COPY %1
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...
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