forked from OSchip/llvm-project
225 lines
6.2 KiB
YAML
225 lines
6.2 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -march=amdgcn -mcpu=tahiti -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
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---
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name: ctpop_s32_ss
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $sgpr0
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; CHECK-LABEL: name: ctpop_s32_ss
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; CHECK: liveins: $sgpr0
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; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
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; CHECK: [[S_BCNT1_I32_B32_:%[0-9]+]]:sreg_32 = S_BCNT1_I32_B32 [[COPY]], implicit-def $scc
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; CHECK: S_ENDPGM 0, implicit [[S_BCNT1_I32_B32_]]
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%0:sgpr(s32) = COPY $sgpr0
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%1:sgpr(s32) = G_CTPOP %0
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S_ENDPGM 0, implicit %1
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...
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---
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name: ctpop_s32_vs
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $sgpr0
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; CHECK-LABEL: name: ctpop_s32_vs
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; CHECK: liveins: $sgpr0
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; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
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; CHECK: [[V_BCNT_U32_B32_e64_:%[0-9]+]]:vgpr_32 = V_BCNT_U32_B32_e64 [[COPY]], 0, implicit $exec
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; CHECK: S_ENDPGM 0, implicit [[V_BCNT_U32_B32_e64_]]
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%0:sgpr(s32) = COPY $sgpr0
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%1:vgpr(s32) = G_CTPOP %0
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S_ENDPGM 0, implicit %1
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...
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---
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name: ctpop_s32_vv
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $vgpr0
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; CHECK-LABEL: name: ctpop_s32_vv
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; CHECK: liveins: $vgpr0
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; CHECK: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; CHECK: [[V_BCNT_U32_B32_e64_:%[0-9]+]]:vgpr_32 = V_BCNT_U32_B32_e64 [[COPY]], 0, implicit $exec
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; CHECK: S_ENDPGM 0, implicit [[V_BCNT_U32_B32_e64_]]
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%0:vgpr(s32) = COPY $vgpr0
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%1:vgpr(s32) = G_CTPOP %0
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S_ENDPGM 0, implicit %1
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...
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---
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name: add_ctpop_s32_v_vv_commute0
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $vgpr0, $vgpr1
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; CHECK-LABEL: name: add_ctpop_s32_v_vv_commute0
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; CHECK: liveins: $vgpr0, $vgpr1
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; CHECK: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; CHECK: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
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; CHECK: [[V_BCNT_U32_B32_e64_:%[0-9]+]]:vgpr_32 = V_BCNT_U32_B32_e64 [[COPY]], [[COPY1]], implicit $exec
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; CHECK: S_ENDPGM 0, implicit [[V_BCNT_U32_B32_e64_]]
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%0:vgpr(s32) = COPY $vgpr0
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%1:vgpr(s32) = COPY $vgpr1
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%2:vgpr(s32) = G_CTPOP %0
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%3:vgpr(s32) = G_ADD %2, %1
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S_ENDPGM 0, implicit %3
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...
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---
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name: add_ctpop_s32_v_vv_commute1
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $vgpr0, $vgpr1
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; CHECK-LABEL: name: add_ctpop_s32_v_vv_commute1
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; CHECK: liveins: $vgpr0, $vgpr1
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; CHECK: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; CHECK: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
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; CHECK: [[V_BCNT_U32_B32_e64_:%[0-9]+]]:vgpr_32 = V_BCNT_U32_B32_e64 [[COPY]], [[COPY1]], implicit $exec
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; CHECK: S_ENDPGM 0, implicit [[V_BCNT_U32_B32_e64_]]
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%0:vgpr(s32) = COPY $vgpr0
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%1:vgpr(s32) = COPY $vgpr1
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%2:vgpr(s32) = G_CTPOP %0
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%3:vgpr(s32) = G_ADD %1, %2
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S_ENDPGM 0, implicit %3
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...
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# Test add+ctpop pattern with all scalars. This should stay scalar.
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---
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name: add_ctpop_s32_s_ss_commute0
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $sgpr0, $sgpr1
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; CHECK-LABEL: name: add_ctpop_s32_s_ss_commute0
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; CHECK: liveins: $sgpr0, $sgpr1
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; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
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; CHECK: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
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; CHECK: [[S_BCNT1_I32_B32_:%[0-9]+]]:sreg_32 = S_BCNT1_I32_B32 [[COPY]], implicit-def $scc
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; CHECK: [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 [[S_BCNT1_I32_B32_]], [[COPY1]], implicit-def $scc
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; CHECK: S_ENDPGM 0, implicit [[S_ADD_I32_]]
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%0:sgpr(s32) = COPY $sgpr0
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%1:sgpr(s32) = COPY $sgpr1
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%2:sgpr(s32) = G_CTPOP %0
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%3:sgpr(s32) = G_ADD %2, %1
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S_ENDPGM 0, implicit %3
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...
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---
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name: add_ctpop_s32_v_vs_commute0
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $vgpr0, $sgpr0
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; CHECK-LABEL: name: add_ctpop_s32_v_vs_commute0
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; CHECK: liveins: $vgpr0, $sgpr0
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; CHECK: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; CHECK: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
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; CHECK: [[V_BCNT_U32_B32_e64_:%[0-9]+]]:vgpr_32 = V_BCNT_U32_B32_e64 [[COPY]], [[COPY1]], implicit $exec
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; CHECK: S_ENDPGM 0, implicit [[V_BCNT_U32_B32_e64_]]
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%0:vgpr(s32) = COPY $vgpr0
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%1:sgpr(s32) = COPY $sgpr0
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%2:vgpr(s32) = G_CTPOP %0
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%3:vgpr(s32) = G_ADD %2, %1
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S_ENDPGM 0, implicit %3
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...
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# SGPR->VGPR ctpop with VALU add
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---
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name: add_ctpop_s32_v_sv_commute0
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $vgpr0, $sgpr0
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; CHECK-LABEL: name: add_ctpop_s32_v_sv_commute0
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; CHECK: liveins: $vgpr0, $sgpr0
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; CHECK: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; CHECK: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
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; CHECK: [[V_BCNT_U32_B32_e64_:%[0-9]+]]:vgpr_32 = V_BCNT_U32_B32_e64 [[COPY1]], [[COPY]], implicit $exec
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; CHECK: S_ENDPGM 0, implicit [[V_BCNT_U32_B32_e64_]]
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%0:vgpr(s32) = COPY $vgpr0
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%1:sgpr(s32) = COPY $sgpr0
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%2:vgpr(s32) = G_CTPOP %1
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%3:vgpr(s32) = G_ADD %2, %0
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S_ENDPGM 0, implicit %3
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...
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# Scalar ctpop with VALU add
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---
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name: add_ctpop_s32_s_sv_commute0
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $sgpr0, $vgpr0
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; CHECK-LABEL: name: add_ctpop_s32_s_sv_commute0
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; CHECK: liveins: $sgpr0, $vgpr0
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; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
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; CHECK: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; CHECK: [[V_BCNT_U32_B32_e64_:%[0-9]+]]:vgpr_32 = V_BCNT_U32_B32_e64 [[COPY]], [[COPY1]], implicit $exec
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; CHECK: S_ENDPGM 0, implicit [[V_BCNT_U32_B32_e64_]]
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%0:sgpr(s32) = COPY $sgpr0
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%1:vgpr(s32) = COPY $vgpr0
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%2:sgpr(s32) = G_CTPOP %0
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%3:vgpr(s32) = G_ADD %2, %1
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S_ENDPGM 0, implicit %3
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...
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---
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name: ctpop_s64_ss
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $sgpr0_sgpr1
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; CHECK-LABEL: name: ctpop_s64_ss
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; CHECK: liveins: $sgpr0_sgpr1
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; CHECK: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
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; CHECK: [[S_BCNT1_I32_B64_:%[0-9]+]]:sreg_32 = S_BCNT1_I32_B64 [[COPY]], implicit-def $scc
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; CHECK: S_ENDPGM 0, implicit [[S_BCNT1_I32_B64_]]
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%0:sgpr(s64) = COPY $sgpr0_sgpr1
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%1:sgpr(s32) = G_CTPOP %0
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S_ENDPGM 0, implicit %1
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...
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